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Fault indicator

About: Fault indicator is a research topic. Over the lifetime, 10057 publications have been published within this topic receiving 143482 citations. The topic is also known as: FCI & power line fault indicator.


Papers
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Patent
11 Oct 2012
TL;DR: In this article, a fault detection circuit is utilized to automatically detect faults in hold-up power storage devices, which includes a holdup monitoring circuit 22 and a memory device 24.
Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit 22 and a memory device 24. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device 18, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power

45 citations

Proceedings ArticleDOI
15 Jun 1994
TL;DR: A microprocessor error behavior function (EBF) is introduced, mapping faults into errors on the functional level, and the results of the emulated bit-flip errors corresponded well to the real results obtained using bit-Flip faults, thus indicating that the injected errors are good approximations of the faults.
Abstract: A microprocessor error behavior function (EBF) is introduced, mapping faults into errors on the functional level. The errors are obtained using a functional model of the processor. By applying the EBF to a fault and instruction distribution, it is possible to obtain the corresponding error distribution. A case study is described, in which (i) the EBFs for simulated bit-flip and pin-level faults are designed and used to compare the bit-flip and pin-level fault models, and (ii) the obtained error distribution for the bit-flip faults is used in an error injection experiment on the functional level to emulate these faults. For the processor used in the case study, it was found that only 9-12% of the bit-flip faults could be emulated using pin-level faults, while a tentative evaluation of the possibility to emulate bit-flip faults with software-implemented fault injection showed that 98-99% could be emulated. Finally, the results of the emulated bit-flip errors corresponded well to the real results obtained using bit-flip faults, thus indicating that the injected errors are good approximations of the faults. >

45 citations

Journal ArticleDOI
01 Jul 2006-Ubiquity
TL;DR: This article aims to present a survey of important software based (or software controlled) fault tolerance literature over the period of 1966 to 2006.
Abstract: This article aims to present a survey of important software based (or software controlled) fault tolerance literature over the period of 1966 to 2006. Nowadays, fault tolerance is a much researched topic. A system fails because of incorrect specification, incorrect design, design flaws, poor testing, undetected fault, environment, substandard implementation, aging component, operator errors or combination of these causes [1,7]. Modern microprocessors having faster and denser transistors with lower threshold voltages and tighter noise margins make them less reliable [6] but such transistors yield performance enhancements [4,5]. At the same time, such transistors render processors more susceptible to transient faults. Transient faults are intermittent faults that are caused by external events or by the environment [7], for examples, energetic particles [84,93] striking the chip or electrical surges [1,3] etc. Though these faults do not cause permanent faults [2], but they may result in incorrect program execution by inadvertently altering processors' states, signal transfers or stored values on registers etc. If a fault of such type affects program's normal execution, it is considered to be a soft error [2,8,85]. Though programming bugs is considered to be an important reason of the most system failures at present but the recent studies suggest that soft errors are increasingly responsible for system downtime. Computing system is becoming more complex and is getting optimized for performance and price but not for availability. This makes soft errors an even more common case. Using denser, smaller and lower voltage transistors has the potential threats to be more susceptible [92] to such increased transient errors. Soft errors

45 citations

Patent
06 Aug 1976
TL;DR: In this article, the reset circuit of a fault indicator is disabled to prevent automatic restoration of the movable target from fault indicating position where it can be observed and manually rest, and a manually operable switch is connected across the reset ciruit and its contacts are closed by permanent magnet means or by manually operating switch means.
Abstract: The reset circuit of a fault indicator is disabled to prevent automatic restoration of the movable target from fault indicating position where it can be observed and manually rest. A manually operable switch is connected across the reset ciruit and its contacts are closed by permanent magnet means or by manually operable switch means.

45 citations

Journal ArticleDOI
TL;DR: In this article, a simple two criteria-based protection scheme is proposed for detection and isolation of high-impedance faults (HIFs) in multi-feeder radial distribution systems.
Abstract: High-impedance faults (HIFs) in electrical power distribution systems produce a very random, non-linear and low-magnitude fault current. The conventional overcurrent (OC) relaying-based distribution system protection schemes find difficulty in detecting such low-current HIFs. In this study, a simple two criteria-based protection scheme is proposed for detection and isolation of HIFs in multi-feeder radial distribution systems. It utilises one-cycle sum of superimposed components of residual voltage for HIF detection and the maximum value of one-cycle sum of superimposed components of negative-sequence current for faulted feeder identification. The performance of the proposed scheme is evaluated for a wide variety of possible test cases by generating data through power systems computer-aided design/electro-magnetic transient design and control software. Results clearly show that the proposed scheme can assist conventional OC relay for detection and isolation of HIFs in distribution systems with any grounding connections in a more reliable and faster way.

45 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202381
2022215
202127
202061
2019116
2018160