Fault indicator

About: Fault indicator is a research topic. Over the lifetime, 10057 publications have been published within this topic receiving 143482 citations. The topic is also known as: FCI & power line fault indicator.

An Efficient Method Based on the Electromagnetic Time Reversal to Locate Faults in Power Networks

Abstract: This paper presents a new method based on the electromagnetic time-reversal (EMTR) theory for locating faults in power networks. The applicability of the EMTR technique to locate faults is first discussed. Using the classical transmission-line equations in the frequency domain, analytical expressions are derived to infer the location of the fault. The accuracy of the proposed method is then discussed in relation to the number of observation points adopted to record the fault-originated electromagnetic transients. Then, this paper illustrates the extension of the proposed method to the time domain. The experimental validation of the proposed method is presented by making reference to a reduced-scale coaxial cable system where real faults are hardware-emulated. Finally, the application of the proposed EMTR-based fault-location method to Electromagnetic Transients Program-simulated cases is presented. The simulated test cases are: a mixed overhead/coaxial cable transmission system and the IEEE 34-bus distribution test feeder. Compared to other transient-based fault-location techniques, the proposed method presents a number of advantages, namely, its straightforward applicability to inhomogeneous media (mixed overhead and coaxial power cable lines), the use of a single observation (measurement) point, and robustness against fault type and fault impedance.

Detection of Demagnetization Faults in Surface-Mounted Permanent Magnet Synchronous Motors by Means of the Zero-Sequence Voltage Component

Abstract: This paper develops and analyzes an online methodology to detect demagnetization faults in surface-mounted permanent magnet synchronous motors. The proposed methodology, which takes into account the effect of the inverter that feeds the machine, is based on monitoring the zero-sequence voltage component of the stator phase voltages. The theoretical basis of the proposed method has been established. Attributes of the method presented here include simplicity, very low computational burden, and high sensibility. Since the proposed method requires access to the neutral point of the stator windings, it is especially useful when dealing with fault tolerant systems. A simple expression of the zero-sequence voltage component is deduced, which is proposed as a fault indicator parameter. Both simulation and experimental results presented in this paper show the potential of the proposed method to provide helpful and reliable data to carry out an online diagnosis of demagnetization failures in the rotor permanent magnets.

A gate-level simulation environment for alpha-particle-induced transient faults

Abstract: Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Modeling and experimental verification of high impedance arcing fault in medium voltage networks

Abstract: A high impedance arcing fault due to a leaning tree in medium voltage (MV) networks is modeled and experimentally verified. The fault is represented in two parts; an arc model and a high resistance. The arc is generated by a leaning tree towards the network conductor and the tree resistance limits the fault current. The arcing element is dynamically simulated using thermal equations. The arc model parameters and resistance values are determined using the experimental results. The fault behavior is simulated by the ATP/EMTP program, in which the arc model is realized using the universal arc representation. The experimental results have validated the system transient model. Discrete wavelet transform is used to extract the fault features and therefore localize the fault events. It is found that arc reignitions enhance fault detection when discrete wavelet transform is utilized