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Fault indicator

About: Fault indicator is a research topic. Over the lifetime, 10057 publications have been published within this topic receiving 143482 citations. The topic is also known as: FCI & power line fault indicator.


Papers
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Journal ArticleDOI
TL;DR: In this paper, three separate fuzzy inference systems are designed for complete protection scheme for transmission line, which is able to accurately detect the fault (both forward and reverse), locate and also identify the faulty phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault inception angle, fault resistances and fault location.
Abstract: This study aims to improve the performance of transmission line directional relaying, fault classification and fault location schemes using fuzzy system. Three separate fuzzy inference system are designed for complete protection scheme for transmission line. The proposed technique is able to accurately detect the fault (both forward and reverse), locate and also identify the faulty phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault inception angle, fault resistances and fault location. The proposed method needs current and voltage measurements available at the relay location and can perform the fault detection and classification in about a half-cycle time. The proposed fuzzy logic based relay has less computation complexity and is better than other AI based methods such as artificial neural network, support vector machine, and decision tree (DT) etc. which require training. The percentage error in fault location is within 1 km for most of the cases. Fault location scheme has been validated using χ2 test with 5% level of significance. Proposed scheme is a setting free method and is suitable for wide range of parameters, fault detection time is less than half cycle and relay does not show any reaching mal-operation so it is reliable, accurate and secure.

92 citations

Patent
27 Oct 2005
TL;DR: In this paper, a method for fault estimation based on residuals (302) of detected signals (301) includes determining an operating regime based on a plurality of parameters, extracting (202) predetermined noise standard deviations of the residuals corresponding to said operating regime and scaling the residual residuals; calculating (203) a magnitude of a measurement vector of the scaled residuals and comparing the magnitude to a decision threshold value; extracting (204) a mean direction and a fault level mapping for each of a pluralityof fault types, based on the operating regime, calculating (205) a
Abstract: A method for performing a fault estimation based on residuals (302) of detected signals (301) includes: determining (201) an operating regime based on a plurality of parameters; extracting (202) predetermined noise standard deviations of the residuals corresponding to said operating regime and scaling the residuals; calculating (203) a magnitude of a measurement vector of the scaled residuals and comparing the magnitude to a decision threshold value; extracting (204) a mean direction and a fault level mapping for each of a plurality of fault types, based on the operating regime; calculating (205) a projection of the measurement vector onto the mean direction of each of the plurality of fault types; determining (206) a fault type based on which projection is maximum; and mapping (207) the projection to a continuous-valued fault level using a lookup table.

92 citations

Patent
30 Apr 1992
TL;DR: In this article, a test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit, which is used for device testing by comparing its outputs to those of a logic circuit and injecting selected faults to aid in device debug.
Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

92 citations

Proceedings ArticleDOI
16 May 1998
TL;DR: This paper introduces a method to detect and identify faults in wheeled mobile robots to use adaptive estimation to predict (in parallel) the outcome of several faults.
Abstract: This paper introduces a method to detect and identify faults in wheeled mobile robots. The idea behind the method is to use adaptive estimation to predict (in parallel) the outcome of several faults. Models of the system behavior under each type of fault are embedded in the various parallel estimators (each of which is a Kalman filter). Each filter is thus tuned to a particular fault. Using its embedded model each filter predicts values for the sensor readings. The residual (the difference between the predicted and actual sensor reading) is an indicator of how well the filter is performing. A fault detection and identification module is responsible for processing the residual to decide which fault has occurred. As an example the method is implemented successfully on a Pioneer I robot. The paper concludes with a discussion of future work.

92 citations

Patent
28 Nov 2000
TL;DR: In this article, a fault interrupter having a microcontroller is provided to detect actual faults and initiate a periodic self-test and provide external notification to the user upon successful or unsuccessful completion of the test.
Abstract: A fault interrupter having a microcontroller is provided to detect actual faults The fault interrupter initiates a periodic self-test and provides external notification to the user upon successful or unsuccessful completion of the test The fault interrupter generates the test signal at a selected time to substantially coincide with the zero-crossing of the AC power source A manual test can also be performed using a manual test switch provided as a direct input to the microcontroller

92 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202381
2022215
202127
202061
2019116
2018160