FET amplifier

Abstract: This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

Abstract: A nonlinear equivalent circuit model for the GaAs FET has been developed based upon the small-signal device model and separate current measurements, including drain-gate avalanche current data. The harmonic-balance technique is used to develop the FET RF load-pull characteristics in an amplifier configuration under large-signal operation. Computed and experimental load-pull results show good agreement.

Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

Abstract: A low noise, multistage microwave transistor amplifier constructed using microwave integrated circuit techniques is disclosed. The illustrated embodiment is a two-stage transistor amplifier which is the basic building block for broadband, high-gain cascades. This amplifier features an interstage network consisting of a very short transmission line which minimizes the size and frequency dependence of the amplifier. This is achieved in the satellite communications band of 3.7 to 4.2 GHz by constructing the amplifier on a suitably low dielectric constant substrate rather than the usual high dielectric constant substrates used in microwave amplifier applications.

Abstract: A DC to DC power converter having reduced switching loss for operation at high frequencies. As disclosed, a buck, or forward, converter includes a first FET as the switching device in series with an inductor and a second FET as the flywheel device. At the common node to which the two FET's and the inductor are connected, there is sufficient capacitance that the FET's may be turned off without appreciable voltage change across the FET's. The value of the inductor is chosen, with respect to the input and output voltages and frequencies of operation involved, to insure that the inductor current polarity reverses each cycle, raising the node voltage to the level of the input voltage, substantially eliminating turn-on losses of the first FET. Control circuitry is provided for regulation of the power converter to control the peak-to-peak current in the inductor and to insure that at least a selected minimum value of the inductor current is present for each cycle of operation of the converter. An over-voltage protection circuit for the output of the converter is also provided.