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FET amplifier
About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.
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TL;DR: The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date and the low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage.
Abstract: This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.
463 citations
TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.
450 citations
TL;DR: In this article, a nonlinear equivalent circuit model for the GaAs FET has been developed based upon the small-signal device model and separate current measurements, including drain-gate avalanche current data.
Abstract: A nonlinear equivalent circuit model for the GaAs FET has been developed based upon the small-signal device model and separate current measurements, including drain-gate avalanche current data. The harmonic-balance technique is used to develop the FET RF load-pull characteristics in an amplifier configuration under large-signal operation. Computed and experimental load-pull results show good agreement.
402 citations
Patent•
13 May 1974TL;DR: In this article, a low noise, multistage microwave transistor amplifier constructed using microwave integrated circuit techniques is disclosed, which is the basic building block for broadband, high-gain cascades.
Abstract: A low noise, multistage microwave transistor amplifier constructed using microwave integrated circuit techniques is disclosed. The illustrated embodiment is a two-stage transistor amplifier which is the basic building block for broadband, high-gain cascades. This amplifier features an interstage network consisting of a very short transmission line which minimizes the size and frequency dependence of the amplifier. This is achieved in the satellite communications band of 3.7 to 4.2 GHz by constructing the amplifier on a suitably low dielectric constant substrate rather than the usual high dielectric constant substrates used in microwave amplifier applications.
295 citations
TL;DR: In this article, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal.
Abstract: In this article, we show that the Doherty amplifier is capable of delivering the stringent requirements of the base station power amplifiers. We explain the operation principles, including both linearity and efficiency improvements, and the basic circuit configuration of the amplifier. Advanced design methods to operate across wide bandwidth and improve the linearity are also described. For verification, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal. These results show that the Doherty amplifier is a promising candidate for base station power amplifiers with wide bandwidth, high efficiency, and linearity
291 citations