Showing papers on "FET amplifier published in 1970"

Digital-to-analog converter with isolated current sources

Abstract: A digital-to-analog converter is disclosed employing a binary weighted current divider connected to the summing junction of an operational amplifier. Current switches selectively couple constant current sources to junctions in the current divider in accordance with binary digits at data input terminals. Each of the current sources consist of an operational amplifier having its output connected to the gate of a field-effect transistor (FET). The source of the FET is connected to a regulated power supply through a high resistance resistor and the drain of the FET is connected to a current switch through an isolation FET having its gate connected to circuit ground by a source of bias voltage and a filter capacitor in parallel. By controlling the regulated voltage to current sources, the analog output signal may be multiplied by a factor to form a product proportional to NS, where N is the number being converted and S is the control signal for the regulated voltage.

Integrated circuit amplifier having an improved gain-versus-frequency characteristic

Abstract: Disclosed is an operational amplifier including an input differential amplifier stage and an output driver stage, with each of the input and output stages having pole compensating capacitance means therein for improving the gain-versus-frequency characteristic of the amplifier. The output pole compensating capacitance means is a high voltage MOS capacitor which splits two of the poles of the amplifier''s transfer function, broadbanding one of the poles and narrowbanding the other of the poles to improve the gain-versus-frequency characteristic of the amplifier. The input pole compensating capacitance means is a low voltage PN junction capacitor which relocates one of the poles of the amplifier''s transfer function to thereby further improve the gain-versus-frequency characteristic of the amplifier while at the same time minimizing the total monolithic integrated circuit die area required for the fabrication of the input and output pole compensating capacitance means.

High-speed mos sense amplifier

Abstract: An improved sense amplifier comprised of an all FET amplifying circuit having means for limiting the voltage swing of the read potential applied thereby to an integrated circuit memory array in sensing the stored ''''1'''' and ''''0'''' memory states. The amplifier includes upper and lower output level-limiting circuits which detect predetermined signal levels in the output signal of the amplifier and cause the impedances at the input of the amplifier to be adjusted to limit the output signal swing of the amplifier to within the predetermined signal leads. In so doing, the memory read potential is also constrained to swing within certain predetermined limits.

Low thermal impedance field effect transistor

Abstract: This disclosure is directed to a Schottky Barrier field effect transistor (FET) having a low thermal impedance and to a process of producing it.

Power amplifier including plurality of push-pull amplifier sections having outputs coupled in parallel

Abstract: A high power semiconductor amplifier, which may be used as the power amplifier of a radio transmitter, includes a plurality of push-pull amplifier sections cooperating to provide the required output power. The amplifier sections are coupled by broadband transformers having ferrite cores and a plurality of inter-wound coils. This affords direct current isolation of the sections and a high degree of coupling as required for broadband operation and provides stable high gain operation with the signals in the two amplifier sections being in very close phase relationship so that they can be combined in-phase for maximum efficiency. The coupling circuit at the output of the sections includes the secondary windings of the transformers connected in parallel circuit branches extending from the reference potential to the output line to reduce the effect of stray reactances. The amplifier is usable over a wide range of frequencies with a minimum of adjustment.

Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors

Abstract: A field-effect transistor (whether junction type or MOS type) has very high input impedance. For those who desire to achieve a higher input impedance, it is often asked `Why aren't FET pairs used as input stages and bipolar transistors used as output stages, since compatible FET and bipolar transistor monolithic structures have been developed?' This correspondence is a study of this question.

Power amplifier including plurality of push-pull amplifier sections coupled by ferrite matching transformers

Abstract: A high power semiconductor amplifier, which may be used as the power amplifier of a radio transmitter, includes a plurality of push-pull amplifier sections cooperating to provide the required output power. The amplifier sections are coupled by broadband transformers having ferrite cores and a plurality of inter-wound coils. This provides direct current isolation of the sections and a high degree of coupling as required for broadband operation, and also results in stable operation and signals in the two amplifier sections which are in close phase relationship so that the outputs thereof can be combined in-phase for maximum efficiency. The coupling circuit at the input and/or the output of the sections includes windings of the transformers in series with a variable reactance element for tuning the same. The amplifier is usable over a wide range of frequencies with a minimum of adjustment.

Linear variable gain circuit utilizing a field effect transistor

Abstract: A linear variable gain circuit which uses a field effect transistor as one branch of two voltage divider networks. The drain terminal of the FET is the midpoint of both voltage divider networks. One of the voltage divider networks is comprised of a resistor and the FET coupled in series with a regulated voltage supply, and the other voltage divider network is comprised of a resistor which is capacitively fed with the relatively AC signal input, and the FET. The signal from the drain terminal of the FET, which is comprised of a relatively DC voltage level and a relatively AC voltage level, and which are responsive to the drain to source resistance of the FET, is fed back as one input to a differential operational amplifier. The other input to the DOA is a relatively DC control signal, in response to which the gain of the circuit is to vary. An AC feedback loop is also provided around the DOA. The DC voltage on the two inputs are compared by the DOA and any DC difference is passed, via a decoupling network, to the gate terminal of the FET to vary the value of its drain to source resistance. The AC signal from the drain terminal at the DOA input is amplified and taken from the DOA output via a capacitor.

Class-BD amplifier circuit

Abstract: An experimental class-BD amplifier circuit is reported, which confirms the previously announced principle of the circuit. Although slightly more complex than the conventional class-AD circuit, filtering problems are simplified, and it may have applications as a high-power amplifier.

Amplifier overload protection circuit

Abstract: An amplifier connected in the voltage follower mode which includes a current-limiting circuit in the feedback loop. The circuit increases in impedance as an overload condition develops and a semiconductor network decreases in impedance under the same conditions so as to preserve the voltage follower mode of the amplifier while uncoupling a load therefrom. The overload protection is also shown with a programmable gain amplifier as well as with another amplifier having overload protection so as to provide a differential input amplifier circuit.

Bio-potential isolated amplifier

Abstract: A floating differential input amplifier is connected through a first field-effect transistor gate to an input winding of a signal transformer. An oscillator is connected to a primary winding of a power isolation transformer which transformer has one secondary winding connected to a rectifier circuit which in turn is connected to supply bias power to the differential amplifier. Another secondary winding of the power isolation transformer is connected to operate the first field-effect transistor gate. The output winding of the signal transformer is connected through a second field-effect transistor gate in series with a coupling capacitor to the input of a potentiometric operational amplifier. The potentiometric operational amplifier is connected to a filter amplifier and an overload detection circuit. An integrating amplifier is connected between the output of the filter amplifier and the input of the potentiometric operational amplifier to provide DC base line correction. The overload detection circuit is connected to operate a field-effect transistor switch connected to the input of the potentiometric operational amplifier and through which the input coupling capacitor can be rapidly charged. A common-mode driver amplifier has one input connected through a resistance network to the inputs of the floating differential amplifier and the other input connected to the common ground of the output circuitry. The output of the common mode driver is connected to an electrostatic cable shield surrounding the input leads connected to the differential amplifier inputs.

Four-phase logic circuit

Abstract: A four-phase logic circuit characterized by a double inverter comprising a series of FETs utilizing unconditional charge and conditional discharge of the output node. Only one FET is interposed in the discharge path. The discharge FET is controlled by a clock pulse connected through a FET which is in turn controlled by the data signal.

Negative impedance amplifier

Abstract: A negative impedance amplifier for a transmission line having two transformers and an amplifier. The size of the transformers is reduced and the resulting losses are compensated by increasing the gain of the amplifier. A negative feedback loop also reduces losses. A capacitor circuit is placed on the line connections to permit remote feeding. The transformers can be connected to the amplifier to provide for either series type or parallel type connection to the line.

Self-balancing push pull amplifier

Abstract: A push pull amplifier including a circuit with an input stage and an output stage having a pair of transistors connected in push pull configuration and cross coupling networks providing negative feedback between the transistors of each pair to maintain the push pull stage in a balanced operating condition, and input and output networks for the circuit including impedance matching transformers and a push pull transformer, the networks being referenced to ground through the impedance matching transformers.

Digital voltmeter apparatus employing a bipolar amplifier having a unidirectional output and a voltage controlled oscillator

Abstract: A voltage to frequency converter serving, for example, as a digital voltmeter which includes a bipolar amplifier responsive to both positive and negative DC inputs and also AC inputs. Coupled to the amplifier is a voltage-controlled oscillator which in combination with a counter provides an indication of the input voltage magnitude. The oscillator is responsive to a single polarity input voltage produced by the bipolar amplifier. To promote the DC stability of the amplifier a chopper amplifier converts all DC to AC which after reconversion to higher level DC is then coupled into the wide-band bipolar amplifier.

Temperature compensated amplifying circuit

Abstract: An integrated circuit differential amplifier incorporates dual current sources having opposite temperature coefficients to compensate the operation of the differential amplifier for variations in ambient temperature. The output of the differential amplifier is applied through a coupling network to a peak-to-peak amplifying detector subject to input impedance variations, with the coupling network including an impedance connected in parallel with the input impedance of the detector circuit and of smaller value.

Linear amplifier circuit

Abstract: A linear amplifier circuit comprising two stages; each stage further comprising two transistors traversed in series by the same current. Cross coupling between the two stages avoid deviations from linearity of the amplifier due to differences in the base-emitter voltages of the transistors. The circuit is suitable for use in integrated circuits.

Linear gain control

Abstract: The gain of an amplifier is controlled by the source-drain impedance of a first field effect transistor having its gate terminal connected to the gate of a second and substantially similar field effect transistor. The second field effect transistor has its source-drain circuit connected in a bridge circuit also including a potentiometer with an adjustable tap providing voltage variations for unbalancing the bridge output. The bridge output operates a differential operational amplifier connected to drive the second field effect transistor for restoring bridge balance. The source-drain impedance of the second field effect transistor, and hence the source-drain impedance of the first field effect transistor, are thereby controlled in proportion to the setting of the aforementioned potentiometer, for adjusting amplifier gain.

Circuit arrangement for a difference amplifier in integrated construction

Abstract: A monolithically integrated difference amplifier having closely adjacent transistors of equal geometrical form and substantially equal properties such that the collector currents in said transistors are equal when said difference amplifier is in a quiescent state is described. The output impedances of the transistors forming the difference amplifier are active impedances, preferably transistors connected in a common base configuration and having their bases connected in common. Coupling between the bases of the active impedance output circuits and the difference amplifier is accomplished by means of an auxiliary difference amplifier.

Television receiver intermediate frequency amplifier circuitry

Abstract: An intermediate frequency amplifier, utilizing a common base transistor amplifier, which changes the intermediate frequency response with gain to improve the weak signal (maximum gain) performance of a television receiver is disclosed. Series and/or parallel resonant circuits are damped by the input impedance of the transistor to increase or decrease the Q of the circuit response.

High gain mos linear integrated circuit amplifier

Abstract: A low power dissipation high load impedance metal-oxide semiconductor field-effect transistor (MOS FET) linear integrated circuit amplifier capable of operation at relatively low power supply voltages with high gain.

Protection circuit for an amplifier

Abstract: A protection circuit for a driver amplifier is provided which senses the absence of current to a driven amplifier and decreases the voltage supplied to the driver amplifier to a safe value thereby preventing damage to the same. The driver amplifier may be a semiconductor (transistor) amplifier and the driven amplifier may be a vacuum tube amplifier which has a warm up period much longer than that of the semiconductor amplifier. The protection circuit protects the semiconductor amplifier during warm up of the tube amplifier, or in the event of failure thereof by reducing the operating voltage applied thereto.

Storage circuit for shift register

Abstract: A shift register storage circuit is provided with first storage means connected to the gate of a first field effect transistor (FET) in which a pulse for another storage means of a subsequent storage circuit is supplied through the same FET independent of the state of the first storage means. In an embodiment, this is accomplished by connecting a source of the pulses to a current flow electrode of the first FET, and connecting this current flow electrode through a capacitor to the gate electrode of the first FET. A second FET serves as an isolating switch between the first FET and the storage means of a subsequent storage circuit. In this arrangement, the pulses may be applied through the first FET independently of the state of the data input at the gate of the FET and without altering the data input.

Voice gated amplifier

Abstract: A voice gated amplifier includes a multi-stage amplifier having a signal path coupling the successive stages of the amplifier. A normally nonconductive field effect transistor placed in series relation with the signal path interrupts the signal path to maintain the amplifier in a standby, nonoperating state. In response to an input signal of predetermined magnitude, a gating circuit renders the field effect transistor abruptly conductive thereby to place the amplifier in an operating state.

Synchronous demodulator employing a common-base transistor amplifier

Abstract: Input signals are coupled in common to the emitter electrodes of a pair of transistors arranged in a differential amplifier configuration, and are synchronously detected by switching signals coupled to the respective transistor base electrodes. The coupling to the emitter electrodes is through a transistor arranged in a common-base amplifier construction, with the signals to be demodulated being applied to the amplifier transistor emitter electrode via an included stabilizing resistor.

Feedback amplifier with bridge-stabilized output impedance

Abstract: An impedance-matching arrangement comprising an operational amplifier with a bridge-stabilized output impedance transfers power between circuits having a common ground. The resulting stable gain and impedance extend over a wide frequency range and minimize impedance-matching power losses. The output impedance of the amplifier is modified to incorporate a Wheatstone bridge, three of whose arms are resistive and the fourth is the output impedance of the amplifier. One bridge diagonal feeds the grounded load circuit and the other supplies symmetrical feedback currents to the respective inputs of the amplifier.

Modified storage circuit for shift register

Abstract: A field effect transistor (FET) shift register storage circuit has a first and second FET series connected from the drain of the first FET to the source of the second FET. A storage capacitor is connected between the gate and source of the first FET. A pulse source is connected to the source of the first FET, and data stored on the capacitor is supplied to the gate of the first FET. A clocking pulse source is connected to the gate of the second FET and is adapted to provide a clocking pulse to the second FET in overlapping relationship to a pulse from the pulse source supplied through the first FET for a storage capacitor of a subsequent storage circuit. In this arrangement, both data input to the storage cell and a pulse for the storage capacitor of a subsequent storage circuit are to the first FET. This storage circuit is both very compact and of simplified structure in integrated form.