Showing papers on "FET amplifier published in 1972"

Drain Feedback - A Novel Feedback Technique for Low-Noise Cryogenic Preamplifiers

Abstract: This paper describes a novel technique of charge restoration - the drain feedback, based on the characteristics of the gate-to-drain junction of the input FET. The restoration charge required at the input of the preamplifier is generated by impact ionization in high-field regions of the FET. Actually the feedback is obtained by regulating the drain voltage according to the input energy count-rate product and consequently adjusting the electric field for the necessary charge generation. In the first part of the paper the principles of impact ionization in semiconductors at cryogenic temperatures are outlined and applied to junction FET's (JFET's) under saturation conditions. Then, the properties of FET gate leakage current generated by impact ionization are analyzed. Finally, the continuous mode of operation of the new feedback method is presented, and results from its application in x-ray spectroscopy with silicon and germanium detectors are given. Superior noise and count-rate performance coupled with simplicity and reliability are the outstanding features of the drain feedback method. It is the first feedback method in which the cryogenic input stage comprises the detector and the FET without the parasitic increases of stray capacitance or light-induced leakage currents characteristic of the other resistorless configurations.

Low noise detector amplifier

Abstract: An amplifier of electromagnetic wave energy in the visible and infrared range includes a photo sensitive detector coupled to a pair of cascoded field-effect transistors arranged to operate at substantial unity gain. A positive feedback path includes the input capacitances of the amplifier reducing and thereby neutralizing the input capacitances of the amplifier. The bandwidth of the amplifier is extended relative to the neutralization of the input capacitances.

Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors

Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.

High power bridge audio amplifier

Abstract: A high power audio amplifier includes four power amplifier sections connected in a bridge, with the power supply connected to one opposite pair of nodes and the load terminals connected to a second opposite pair of nodes One of the load terminals may be connected to a ground reference potential and the power supply is floating with reference to ground First and second drive amplifiers are provided, with each of the drive amplifiers being connected to the two power amplifier sections connected to one load terminal The input signal to be amplified is applied to one input of the first drive amplifier and a feedback signal from the load terminal which is not connected to ground is connected to the second input thereof The second drive amplifier receives either the input signal or the signal from the load terminal, and compares the same with the supply potential to balance the bridge To protect the transistors of the power amplifier sections, the currents in the transistors of the amplifier sections driven by the second drive amplifier are sensed and used to control the first drive amplifier, to thereby protect the transistors in all of the power amplifier sections Auxiliary protection circuits are provided for the transistors in the power amplifier sections coupled to each drive amplifier

Current mirror amplifiers

Abstract: A current mirror amplifier for combining the output currents of an MOS source-coupled differential amplifier comprises first and second bipolar transistors having parallelled base-emitter circuits including emitter degenerative resistors. A similar resistor judicially placed in the collector circuit of one of these bipolar transistors ensures that the differential amplifier will not exhibit an offset potential between its input terminals caused by its component devices being subjected to different conditions of quiescent drain biasing when the differential amplifier supplies its combined output currents by direct coupling to a subsequent grounded-emitter amplifier stage.

Bootstrap fet driven with on-chip power supply

Abstract: A bootstrap FET driver amplifier having a precharged relatively higher gate voltage and a relatively lower drain voltage obtained from a common power source. The gate voltage is derived from recurrent pulses produced by an on-chip FET free-running multi-vibrator and a voltage multiplier circuit powered from said power source. The pulse width of the recurrent pulses varies as an inverse function of the transconductance of the on-chip FETs and as a direct function of the threshold voltage of the on-chip FETs. The pulse width controls the charging time of a voltage booster capacitor in the voltage multiplier circuit whereby the amplitude of the boosted voltage is a direct function of the pulse width. The boosted voltage is applied to the gate of the bootstrap FET driver amplifier.

Transducer amplifier with automatic balance

Abstract: An amplifier for strain gages and other transducers in quarter, half or full bridge configurations provides an analog output suited for measurement, control or display purposes. The amplifier includes temperature compensation and automatic zero balance, the former realized from the voltage-temperature characteristic of a silicon PN junction used to affect the offset of an integrated circuit amplifier stage. The signal for zero balance is derived from the amplifier output, sampled and retained in an analog to digital converter and reconverted to analog form for application to a stage of the amplifier in opposition to the measurement signal, resetting for zero balance being under manual control.

Light amplifier for use in optical communication system

Abstract: A light amplifier comprising a first photo transistor for converting an optical input applied by way of an optical transmission line into an electrical signal, a comparator amplifier connected to the first photo transistor for receiving the output signal of the photo transistor as one of the two inputs thereto, a first and a second light emitting diode emitting light depending on the output current of the comparator amplifier, and a second photo transistor for converting the optical output signal of the first light emitting diode applied through a pair of polarizers into an electrical signal and applying this electrical signal in negative feedback fashion to the comparator amplifier as the other input thereto. The output current of the comparator amplifier is controlled so that coincidence is attained between the output signals of the photo transistors, and the optical output signal of the second light emitting diode is delivered to another optical transmission line as an amplified optical output.

High frequency field effect transistor switch

Abstract: An improved field effect transistor (FET) switching circuit for sampling an analog input in response to a control pulse at extremely fast turn-on and turn-off times. the FET operating potential is obtained from a constant voltage source rather than the control signal. A diode is provided between the FET gate and the signal source and also a diode is provided between the FET gate and the control pulse source; the diodes retain sufficient stored charge to completely discharge the FET gate to channel capacitance during switching.

Fet interface circuit

Abstract: The specification describes an FET circuit for converting bipolar transistor signal levels to field effect transistor (FET) signal levels and includes a capacitor, a signal FET, a load FET and a feedback FET. The feedback FET is connected as a diode between the output of the circuit and the input to the signal FET biasing the input of the signal FET to a predetermined potential level that is slightly in excess of its threshold voltage drop.

Fet threshold compensating bias circuit

Abstract: Disclosed is a bias circuit that eliminates the adverse effect of threshold voltage variations on field effect transistor (FET) circuit performance. The gate electrode of a load device is maintained at one threshold level above the supply potential regardless of threshold voltage variations, optimizing the linear impedance characteristics of the load device and the power/performance characteristics of the resultant FET circuit.

Field effect transistor push-pull driver

Abstract: An integrated circuit FET push-pull driver includes a first FET boot-strap circuit for charging the driver output node to a value below the driver supply voltage. A second FET boot-strap circuit adds additional charge to the output node to drive the output node to the supply voltage. An FET clamping circuit functions to prevent the additional charge from leaking off through the first boot-strap circuit.

Circuit using dynamic high impedance load

Abstract: An amplifier comprising a series of field effect transistors is connected to a dynamic high impedance load. The output of the amplifier preferably is taken from the last stage of that load. The dynamic high impedance load may be a constant current source consisting of at least three field effect transistors.

Integrated differential amplifier

Abstract: An integrated difference amplifier comprising a gain controlled first differential amplifier arrangement which is suitable for amplifying signals of low value and a satisfactory signal-tonoise ratio. In case of an increasing signal intensity the first differential amplifier arrangement is cut off and the signal amplification is taken over by a second differential amplifier arrangement which is suitable for processing large signal amplitudes.

Capacitive-discharge timing circuit using comparator transistor base current to determine discharge rate

Abstract: A timing capacitor is connected to one of the input terminals of a differential, transistor amplifier which forms part of an operational amplifier. The capacitor is controllably discharged through the base-to-emitter path of one of the differential transistors. An output signal of programmable duration is thereby derived from the operational amplifier according to the discharge duration of the capacitor.

Low cost digital to synchro converter

Abstract: A digital to analog (D/A) converter suitable for application to digital to synchro (D/S) conversion comprises serial MOS FET (Metallic Oxide Semiconductor-Field Effect Transistor) switches and an inverting amplifier, or buffer, to compensate for variations in FET resistance in the ON state. A reference voltage of a given polarity is gated ON in one FET and inverted in polarity in an amplifier with a gain of 1.0 for input to a bank of FET switches associated with a binary resistance network, accomplishing directly the conversion of digital data to an analog equivalent output. The reference voltage thereby gated in the first FET with one polarity is subsequently gated in the second FET switches, of the bank associated with the network, and with the opposite polarity, such that a nearly constant resistance path is afforded from the reference voltage to the output of the second FET switches. Employing identical FET switches throughout the D/A converter, the non-linear properties of the FET switches are compensated regardless of reference voltage polarity. To improve further the accuracy of D/A conversion of the invention, an input resistance is selected for the inverting amplifier equal in value to the resistance of the most significant bit resistor. Compensating resistors affording resistance equalization are provided for at least a few of the next, most significant bit positions resulting in highly accurate digital to analog and digital to synchro conversion using low cost MOS FET switches with high ON resistance.

Transconductance reduction using multiple collector pnp transistors in an operational amplifier

Abstract: A differential input stage for an integrated circuit operational amplifier, having low transconductance, yet having high frequency response. The low transconductance of the differential input stage is achieved without sacrificing frequency response by using multiple collector lateral PNP transistors, whereby only a fraction of the total PNP transistor current flows in the collector circuit and contributes to the transconductance of the differential amplifier stage.

Fet analog multiplex switch

Abstract: An FET analog switching circuit, including an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between the input terminal and the output terminal, one of the first and second FET''s being an N type and the other being a P type, and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on the first FET and of the opposite polarity to the gate of the second FET to simultaneously turn on the second FET.

Amplifier for use in communication systems

Abstract: An amplifier for use in communication systems in which the output lines supply power to the amplifier which can operate from either polarity of supply voltage which may also be a relatively low voltage. The amplifier receives an input signal and applies the signal to said pair of lines. In one embodiment of the amplifier it can operate at high gain in response to an input signal and low gain in absence of an input signal to provide suppression of background noise. Another embodiment provides control of the amplifier gain as a function of operating current to more closely match the output characteristics of carbon microphones. The amplifier disclosed is particularly suitable for integration into a silicon monolithic bipolar circuit.

A.c.-d.c. amplifier system

Abstract: A wide-band a.c., stable d.c., amplifier system employing a wide-band operational amplifier and an integrator-feedback high-gain essentially d.c.-amplifying operational amplifier. The system provides uniform gain over a wide band of frequencies, including low frequencies and d.c., with precise stability useful for instrumentation. Indication of abnormal operation is available.

Memory circuit using variable threshold level field-effect device

Abstract: A memory circuit using a variable threshold level field-effect device, such as a metal-silicon nitride-silicon dioxide-semiconductor field-effect transistor (MNOS FET) or a metal-aluminum oxide-silicon dioxide-semiconductor (MAOS) FET, as the memory transistor connected in series with at least one metal-insulator-silicon (MIS) FET. An addressing signal is supplied to the MIS FET to address the particular memory transistor connected thereto. In this condition, a signal for reading or writing information by changing the characteristics of the memory transistor can be applied to the gate of the latter transistor.

Design Considerations of a 3.1 - 3.5 GHz GaAs FET Feedback Amplifier

Abstract: Recent GaAs FET devices have exhibited promising capabilities for microwave amplification. Circuit designers, however, found two problems with the FET applications, namely, the characteristically high input/output impedances are difficult to match into a 50/spl Omega/ system and the potential instabilities that exists at frequencies below 4 GHz. This paper describes development work done on feedback circuits in designing an unconditionally stable FET amplifier in the 3.1 - 3.5 GHz frequency range by using conventional microstrip techniques, and also investigates the effect of feedback components on noise and output capabilities.

Rf amplifier control system

Abstract: Two RF amplifiers may be selectively coupled and decoupled between a single antenna and a single mixer by switching circuits associated with each amplifier. A PIN diode is connected between the antenna and the input of each RF amplifier. A switching arrangement includes a complementary pair of transistors, one connected between a source of DC operating voltage and the amplifier and the other connected between the first transistor and the PIN diode. When the first transistor is biased to conduction by an appropriate control voltage, the associated RF amplifier is activated and DC current flows through both transistors causing the PIN diode to present a low impedance to RF signals from the antenna. When the first transistor is biased to cutoff by an appropriate control voltage, no current flows in the transistors inactivating the RF amplifier and causing the PIN diode to present a high impedance to RF signals from the antenna.

A C-Band All Ferrite Integrated Wideband High Power GaAs Avalanche Diode Amplifier

Abstract: A C-band 4-stage, 20 dB gain, 3-watt 25% bandwidth all ferrite substrate integrated GaAs avalanche diode amplifier is developed. The design procedure, as well as the amplifier performance including amplifier phase characteristics, is described. A power combining circuit which increases the output power capability by a factor of two is included in the output stage.

A low impedance field effect transistor

Abstract: A junction field effect transistor having non-saturation characteristics like a vacuum tride has been successfully developed. Its output impedance can be decreased to 8 ohms so that it will serve in audio applications or as an impedance transformer. The geometrical structure of this FET is analogous to that of a triode tube and is based on the idea of controlling the resistance between drain and source by a potential applied to a grid-like gate structure. Design considerations that avoid saturation of the drain current will be discussed.

Amplifier circuit using complementary symmetry transistors

Abstract: An amplifier circuit includes two sets of complementary-symmetry transistors. The base of the PNP transistor of the second complementary symmetry stage is connected to a junction between the emitters of the NPN and PNP transistors of the first stage. The base of the NPN transistor of the second stage is connected to an impedance element and to the load. The impedance element is connected in series with the collector of a transistor in a driver circuit.

Field effect transistor linear amplifier with clocked biasing means

Abstract: A self-biasing MOS linear amplifier is provided with improved means for maintaining the circuit biased to its linear amplification range. That means comprises a clocked feedback FET operatively connected between the output and input terminals and adapted to charge a storage capacitor at the input during a first clock interval, the bias level applied at the input being a function of the operating characteristic of the switching FET. The storage capacitor is effective to maintain the device so biased throughout the remainder of the clock cycle.

Amplifier with protective energy limiter circuit components

Abstract: A direct coupled state high fidelity amplifier incorporates an energy limiting circuit to provide protection against the user accidentally overloading and damaging the amplifier. The energy limiting circuit is designed so that the output transistors of the amplifier cannot be required to carry a specified amount of power for a longer period than would permit their safe operation without damage. This is done by examining and limiting the time integral of the product of voltage and current, i.e., energy, that the output transistors of the amplifier absorb. The result of using the energy limiting circuit is an increase in the efficiency of utilization of the output transistors, which in turn allows for an increase in power supplied by the amplifier to other components of the stereo system, while reducing the number of output transistors required.

Integrated semiconductor device or element

Abstract: In order to maintain the source voltage constant in an operating MOST amplifier that tends to drift in a thermally static environment a differential amplifier is connected to the source terminal of an identical auxiliary MOST amplifier operating under the same initial bias conditions as the operating MOST amplifier. A heater connected to the output of the differential amplifier alters the thermal operating point of both the MOST amplifier and the auxillary MOST amplifier until the source voltage of the auxillary MOST amplifier reverts to its original value.