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Showing papers on "FET amplifier published in 1977"


Journal ArticleDOI
H. Carlin1
TL;DR: In this paper, a new idea for treating the broadband matching of an arbitrary load to a resistive generator leads to a simple technique for the design of a lossless 2-port equalizer.
Abstract: A new idea for treating the broad-band matching of an arbitrary load to a resistive generator leads to a simple technique for the design of a lossless 2-port equalizer. The method is a numerical one, and only utilizes real frequency (e.g., experimental) load impedance data. No model or analytic impedance function for the load is necessary. Nor is the equalizer topology or analytic form of the system transfer function assumed. The arithmetic is well conditioned and the intricacies of gainbandwidth theory are bypassed. An example comparing the method with analytic gain-bandwidth theory is given. Two examples proceeding directly from experimental data are presented. One is the broad banding of a microwave avalanche diode reflection amplifier. The other is the gainbandwidth equalization of a microwave FET amplifier for gain taper and impedance mismatch.

249 citations


Patent
22 Aug 1977
TL;DR: In this article, a complementary symmetric amplifier is described, where a CMOS inverter has its P-channel MOSFET paralleled by the emitter-to-collector path of a simultaneously conductive PNP bipolar transistor.
Abstract: A complementary-symmetry amplifier is described, wherein a CMOS inverter has its P-channel MOSFET paralleled by the emitter-to-collector path of a simultaneously conductive PNP bipolar transistor and has its N-channel MOSFET paralleled by the emitter-to-collector path of a simultaneously conductive NPN bipolar transistor. The amplifier switches very rapidly due to the high transconductances of the bipolar transistors, while the MOSFET's permit the output terminal of the amplifier to swing over the full range of available supply potential.

52 citations


Patent
17 Jun 1977
TL;DR: In this article, a push-pull power amplifier for amplifying an input signal is described where anti-phase signals are generated from the input signal using a first hybrid junction for driving a pair of transistors and where output signals are combined in-phase on an output line by using a second hybrid junction.
Abstract: A push-pull power amplifier for amplifying an input signal is described where anti-phase signals are generated from the input signal using a first hybrid junction for driving a pair of transistors and where anti-phase transistor output signals are combined in-phase on an output line by using a second hybrid junction. An independent port may be added to the hybrid junction for isolating and terminating even order harmonics and even order intermodulation products.

29 citations


Proceedings ArticleDOI
01 Oct 1977
TL;DR: In this paper, the design and characterization of octave coverage amplifier modules over X and J-band frequencies up to l8GHz is described. But the authors do not consider the use of FET matching circuits.
Abstract: Lumped-element design, fabrication and characterization has been extended for MIC requirements up to l8GHz. Spiral or loop inductors and overlay or interdigital capacitors have been measured at appropriate frequencies leading to satisfactory equivalent circuits. Variations in parasitic reactances and Q-factor with frequency, substrate dielectric constant and component geometry are presented. Particular applications include filter networks and FET amplifier matching circuits, the latter enabling octave coverage amplifier modules over X and J-band frequencies to be realised.

23 citations


Patent
25 Feb 1977
TL;DR: In this article, a preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement.
Abstract: A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

19 citations


Patent
25 Oct 1977
TL;DR: In this paper, a microwave frequency discriminator consisting of a field effect transistor (FET) amplifier, a variable capacitor and a biasing circuit was proposed to match the impedance of the FET output to the input of the detector.
Abstract: A microwave frequency discriminator comprising a field effect transistor (FET) amplifier including an electronically variable capacitor (varactor), a biasing circuit and a detector. The FET is biased to generate an output RF signal within a predetermined frequency bandwidth in response to an input RF signal of substantially constant power level. The variable capacitor is biased to electronically provide a predetermined impedance to the transistor to augment the frequency roll-off characteristic of the FET. The biasing circuit is used to electronically match the impedance of the FET output to the input of the detector. At such impedance conditions the dc output voltage of the detector varies substantially linearly throughout the frequency bandwidth as a function of the frequency of the input RF signal, approximating the characteristic of a frequency discriminator.

19 citations


Patent
Adel A. A. Ahmed1
14 Feb 1977
TL;DR: In this article, the potentials appearing across the principal conduction paths of master and slave transistors are maintained substantially the same, and a differential-input, single-ended output amplifier is connected as a non-inverting amplifier in the direct-coupled feedback connection.
Abstract: A current mirror amplifier in which the potentials appearing across the principal conduction paths of its master and slave transistors are maintained substantially the same. This is done by a differential-input, single-ended output amplifier, which is connected as a non-inverting amplifier in the direct-coupled feedback connection that conditions the master transistor to conduct applied input current via its principal conduction path.

19 citations


Patent
24 Jan 1977
TL;DR: In this paper, an amplifier circuit for the unadulterated transmission of phase information of a supplied ac voltage signal over a large dynamic range includes a series connection of a series of similar amplifier stages each of which is followed by a symmetrical limiter.
Abstract: An amplifier circuit for the unadulterated transmission of phase information of a supplied ac voltage signal over a large dynamic range includes a series connection of a series of similar amplifier stages each of which is followed by a symmetrical limiter. The amplifier operates as a logarithmic amplifier for maintaining the amplitude information of the supplied ac signal. Each of the amplifier stages comprise an emitter-base transistor amplifier circuit having negative feedback and an output circuit which contains a resonant circuit which is strongly damped by an attenuating resistor and whose capacitance is formed by a trimmer capacitor connected in parallel to a pair of diodes. The diodes are connected in anti-parallel relation to one another and represent the limiter. The capacitance is adjustable for purpose of impedance adjustment and is set in such a manner that the resultant resonant circuit impedance is capacitive.

18 citations


Patent
03 Oct 1977
Abstract: A microwave power limiter for generating an output RF signal of substantially constant power level in response to an input RF signal of varying power level comprises a dual gate field effect transistor (FET). The FET is biased such that the RF power output variation is small compared to the input power variation in the saturation region. A number of FET cascaded stages may be utilized to reduce this power output variation. A small signal amplifier including a number of FET cascaded stages may be employed in the limiter to increase the power level to that gain or drive level compatible with the saturated FET stages.

17 citations


Patent
06 Apr 1977
TL;DR: In this paper, a self-biasing low input impedance differential amplifier for current mode applications requiring wide bandwidth with response down to DC is proposed, where a shunt-shunt differential mode feedback system in combination with a seriesshunt common-mode feedback system is connected between an input amplifier stage and an output amplifier stage.
Abstract: A self biasing low input impedance differential amplifier for current mode applications requiring wide bandwidth with response down to DC. A shunt-shunt differential mode feedback system in combination with a series-shunt common mode feedback system is connected between an input amplifier stage and an output amplifier stage. An additional shunt-series common mode feedback signal is applied to the input stage to short out the common mode component of the amplifier input signal and minimize input signal drift. High open loop gain in the differential feedback loop provides low impedance amplifier inputs.

17 citations


Patent
01 Aug 1977
TL;DR: In this article, an acoustic transducer including an improved electret assembly mounted in an improved case and having an electronic amplifier circuit comprising FET transistors is described, and the electronic circuit further includes means for protecting the transistors against current surges.
Abstract: The present invention relates to an acoustic transducer including an improved electret assembly mounted in an improved case and having an electronic amplifier circuit comprising FET transistors. The electronic circuit further includes means for protecting the FET transistors against current surges.

Patent
Thomas J. Robe1
09 Mar 1977
TL;DR: In this article, a differential-input amplifier has an input terminal connected to the emitter electrode of a transistor and resistances are provided for sensing the flow of current through the principal conduction path of each transistor.
Abstract: Each half of a differential-input amplifier stage has an input terminal connected to the emitter electrode of a transistor. Resistances are provided for sensing the flow of current through the principal conduction path of each transistor. Output signal current for the stage is taken from the collector of at least one of the transistors and applied to the input of a following one of a cascade connection of amplifier stages. Voltage comparator means sense the drop in potential across one of the resistances caused by reduction of current in one half of the diffferential-input amplifier to increase the current available to the other half. This increases the output signal current available to charge or to discharge capacitance in the stage(s) cascaded after the diffferential-input amplifier, increasing the slew rate of the cascade.

Journal ArticleDOI
TL;DR: In this paper, a two-layer short-channel FET structure is proposed to improve amplifier linearity and enhance unity-current-gain (UCCG) frequency, which can effectively reduce the device noise arising due to hot electrons.
Abstract: The characteristics of a proposed two-layer short-channel FET structure are analyzed and compared with those of the conventional structure. The new structure provides improved amplifier linearity and enhanced unity-current-gain frequency. Suitable combinations of doping in the two layers and gate-to-drain electrode separation can effectively reduce the device noise arising due to hot electrons.

Patent
25 Nov 1977
TL;DR: Disclosed as discussed by the authors is a low noise amplifier capable of handling large signals without significant distortion and which is particularly useful as the first electronic stage in hydrophone array systems utilizing piezoelectric sensor elements.
Abstract: Disclosed is a low noise amplifier capable of handling large signals without significant distortion and which is particularly useful as the first electronic stage in hydrophone array systems utilizing piezoelectric sensor elements. The amplifier comprises three stages. The first stage uses an input field effect transistor (FET), which is protected against overload by very low leakage current diodes, and which acts as a voltage-to-current converter. The second stage comprises a junction transistor connected in a common emitter configuration which acts as a current-to-voltage converter. The third stage is a further junction transistor connected as an emitter follower. The overall gain of the amplifier is controlled by a feedback connection from the third stage to the first stage. The second and third stages are powered by a bipolar power supply. The second stage junction transistor has its emitter connected to the positive supply voltage by a pair of diodes forward biased by the supply voltage to provide low distortion and fast overload recovery. The third stage includes a second field effect transistor (FET), in series with the junction transistor of the third stage, which allows enhanced output drive capability. Resistors are connected in series with the base and collector of the third stage junction transistor to provide output short circuit protection.

Patent
31 Aug 1977
TL;DR: In this paper, a low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (V DD ) and by connecting to the second isolation Fet (T4) so it can switch from its on-state to its off-state.
Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (V DD ) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.

Patent
Sickert Klaus Dipl Ing1
14 Apr 1977
TL;DR: Binary processing LSI circuitry consists of stages each of which has a load FET in series with connecting and active FETs and is controlled by a separate clock pulse as discussed by the authors, the clock pulses to consecutive stages should be mutually inverse, consecutive stages (3, 4) have linking FET (T2, T3, T6, T7) of different conduction type from the load transistors (T4, T5) The wall transistors are connected alternately to the voltage source terminals
Abstract: Binary processing LSI circuitry consists of stages each of which has a load FET in series with connecting and active FETs and is controlled by a separate clock pulse One main terminal of the load FET is connected to a capacitor, and is the stage output, connected to the input of at least one other stage To speed signal processing the clock pulses to consecutive stages should be mutually inverse, consecutive stages (3, 4) have linking FET (T2, T3, T6, T7) of different conduction type from the load transistors (T4, T5) The wall transistors are connected alternately to the voltage source terminals

Patent
20 Dec 1977
TL;DR: In this paper, a transistor amplifier in which collector to emitter voltages and currents are kept constant, particularly in the power output stages of the amplifying devices for minimizing distortion due to changes in the transistor beta, the essential form of distortion in amplifiers.
Abstract: A transistor amplifier in which collector to emitter voltages and currents are kept constant, particularly in the power output stages of the amplifying devices for minimizing distortion due to changes in the transistor beta, the essential form of distortion in amplifiers. High fidelity low power output current from a cascoded transistor amplifier is fed through a load to a second, high power, amplifier having constant current and less than unity gain, with an output summed with the output of the first amplifier such that the output of the first low power amplifier is the signal bearing portion and the output of the second amplifier serves as a current bootstrap, increasing the effective impedance of the load as seen by the first amplifier.

Proceedings ArticleDOI
21 Jun 1977
TL;DR: In this article, the authors describe a five-stage amplifier with three stages operating in the negative resistance mode with 2 GHz of bandwidth, the final two stages are injection-locked and the total amplifier gain is 33 dB.
Abstract: A technology development is described which has clearly advanced the state-of-the-art in high power, high performance solid state amplifiers. Five watts of output power at 37 GHz were achieved with a five-stage amplifier. Three stages operate in the negative resistance mode with 2 GHz of bandwidth, the final two stages are injection locked. The total amplifier gain is 33 dB. High efficiency power combining is used in the two power stages. Extensive use has been made of computer aided design, both in the negative resistance amplifier development and in the modeling and optimization of the multiple diode power combining structures. Novel broadband circulators couple the individual stages and provide interstage isolation with insertion loss levels of 0.1 dB per path. The entire amplifier, including diode current regulators, is enclosed in a housing 6 x 8 x 3 inches in size, and weighs 9 pounds.

Patent
Kenzo Tanabe1, Masashi Kanno1
09 Nov 1977
TL;DR: In this article, an integrated front end circuit for a VHF receiver including a high frequency grounded base amplifier, a mixer having a differential type amplifier and a constant current type oscillator, and a bias circuit is presented.
Abstract: The present invention is an integrated front end circuit for a VHF receiver including a high frequency grounded base amplifier, a mixer having a differential type amplifier, a constant current type oscillator, and a bias circuit. In the mixer, a resistor is inserted between common emitters of the transistors of a differential amplifier and the collector of a constat current transistor driving the differential amplifier. In order to keep the oscillation frequency constant during a change in source voltage, there is provided a certain relation between the change in source voltage and the driving current of the oscillator by means of a bias circuit. The collectors and bases of the transistors used for the high frequency amplifier, the differential amplifier and the oscillator use the same D.C. potential. The integrated front end circuit of the invention may be used, for example, as the front end of an FM portable radio receiver, and it is very desirable for practical use because it realizes sure operation even at a low voltage.

Patent
Hendricus Visser1
19 Dec 1977
TL;DR: In this article, a multi-stage amplifier with delayed AGC-control gain control in one stage is effected by means of controllable current distribution between control transistors, and the take-over point of the delayed GAC for a previous stage is determined from the ratio between the direct currents of said control transistor.
Abstract: In a multi-stage amplifier with delayed AGC-control gain control in one stage is effected by means of controllable current distribution between control transistors. The take-over point of the delayed AGC for a previous stage is determined from the ratio between the direct currents of said control transistors.

Patent
25 Feb 1977
TL;DR: In this paper, a single-chip memory-sense amplifier for a data processing system is described, which is intended for use with memory fabricated from N-channel MOS technology and formed on a single monolithic integrated circuit chip.
Abstract: A single-chip memory-sense amplifier for a data processing system. There is disclosed a sense amplifier (level converter) and bus driver for use in a data processing system, to receive signal inputs from main memory and to drive a memory bus connecting output of the sense amplifier to the CPU. This sense amplifier is intended for use with memory fabricated from N-channel MOS technology. The circuitry of the sense amplifier is fabricated from bi-polar technology and formed on a single monolithic integrated circuit chip. The biasing scheme employed within the circuitry of the sense amplifier provides reliable operation, by making the amplifier relatively insensitive to power supply variations.

Patent
14 Jan 1977
TL;DR: In this article, a linear output amplifier for a charge coupled device arrangement was proposed, in which the amplifier has a field effect switching transistor serially connected to a load element, the connection point between the transistor and the load element being the output of the amplifier and the gate terminal of the transistor being the input of amplifier.
Abstract: A linear output amplifier for a charge coupled device arrangement in which the amplifier has a field effect switching transistor serially connected to a load element, the connection point between the transistor and the load element being the output of the amplifier and the gate terminal of the transistor being the input of the amplifier. The input of the amplifier is connected to the charge coupled device arrangement by either connecting it to the output diffusion zone of the same or by connecting it to a control electrode of the charge coupled device arrangement. Between the output of the amplifier and the input of the amplifier an additional transistor is provided with the aid of which the input can be connected to the output. Preferably, the load element is a field effect transistor and the load resistance which it provides can be varied by connecting a voltage source of desired amplitude to the gate terminal thereof.

Patent
07 Apr 1977
TL;DR: In this article, a controlled oscillator comprises an amplifier including an active device, a filter network arranged in a feedback loop of the amplifier for providing regenerative feedback to sustain oscillation, and a source of control signals.
Abstract: A controlled oscillator comprises an amplifier including an active device, a filter network arranged in a feedback loop of the amplifier for providing regenerative feedback to sustain oscillation of the amplifier, and a source of control signals. A common load network is provided for oscillatory signals produced by the amplifier and for the control signals, and is coupled to the filter network. The common load network comprises amplifying means having a low input impedance relative to an impedance presented to the oscillatory and control signals by parasitic capacitances which may be associated with respective output terminals of the active device and the source of control signals.

Patent
06 May 1977
TL;DR: In this paper, a non-linear direct-current amplifier for linearizing the output characteristic of a measuring transducer, comprising a main amplifier of which the overall gain is determined by means of one or more nonlinear operational amplifier elements of which individual outputs are connected by way of respective summing resistors with the input of the main amplifier.
Abstract: A non-linear direct-current amplifier in particular for linearizing the output characteristic of a measuring transducer, comprising a main amplifier of which the overall gain is determined by means of one or more non-linear operational amplifier elements of which the individual outputs are connected by way of respective summing resistors with the input of the main amplifier, the input of each operational amplifier element being connected with the tapping of a resistive voltage divider connected between the output of the main amplifier and a reference potential source. Depending on the construction and connection of the operational amplifier elements, amplifier characteristics having increasing, decreasing or both types of slopes can be approximated by rectilinear sections.

Proceedings ArticleDOI
S. Fukuda1, M. Kitamura1, Y. Ara1, I. Haga1
21 Jun 1977
TL;DR: In this paper, a microwave amplitude limiter with low AM-to-PM conversion using a class A GaAs FET amplifier was proposed for use with 200 Mbits/sec 4-phase PSK signals or 2700-channel FDM-FM signals.
Abstract: This paper describes a new microwave amplitude limiter with low AM-to-PM conversion using a class A GaAs FET amplifier. It has been experimentally established that this limiter is applicable for use with 200 Mbits/sec 4-phase PSK signals or 2700-channel FDM-FM signals.

Patent
16 Mar 1977
TL;DR: In this article, an audio- or low-frequency power amplifier comprises a pair of output transistors which are opposite in a conduction type to each other and connected in a complementary push-pull circuit configuration.
Abstract: An audio- or low-frequency power amplifier comprises a pair of output transistors which are opposite in a conduction type to each other and connected in a complementary push-pull circuit configuration in which an impedance element is connected between the bases of the paired output transistors whose bases are adapted to be applied with an input signal while the output signal of the amplifier is derived from the coupled emitters of the output transistors. The amplifier further includes a current stabilizer transistor having a base-emitter junction across which a fixed bias voltage is applied and a collector, the current from which is supplied to the impedance element thereby to provide a bias voltage for the paired output transistors. A first resistor is connected between the emitter of the current stabilizer transistor and one electrode or pole of a first d.c. power source while a second resistor is connected between the emitter of the current stabilizer transistor and the other pole of the d.c. source, thereby to maintain constant the bias voltages applied to the paired output transistors.

Patent
27 Apr 1977
TL;DR: In this article, a dual mode amplifier for use as the output amplifier of a sample and hold circuit is described, where the amplifier characteristics are optimized for best slew rate and transient performance.
Abstract: There is disclosed a dual mode amplifier for use as the output amplifier of a sample and hold circuit. The dual mode amplifier described by the invention is controlled by a sample and hold gate. In one of its modes the characteristics of the amplifier are optimized for best slew rate and transient performance, while in the other mode the amplifier characteristics are optimized for settling time.

Proceedings Article
01 Sep 1977
TL;DR: In this paper, the authors describe the computer-aided design and physical realization of a 1 GHz bandwidth monolithic integrated differential amplifier using silicon bipolar transistors, which has a 3 dB cutoff frequency of 1.2 GHz and a noise figure of about 6 dB.
Abstract: This paper describes the computer-aided design and physical realization of a 1 GHz bandwidth monolithic integrated differential amplifier using silicon bipolar transistors. Experimental measurements are given which show that the amplifier has a 3 dB cutoff frequency of 1.2 GHz and a noise figure of about 6 dB.

Proceedings ArticleDOI
21 Jun 1977
TL;DR: A push-pull power amplifier, in which the required anti-phase RF voltages result from the use of inherently symmetric and frequency-independent slot line tees, is described in this paper.
Abstract: A push-pull power amplifier, in which the required anti-phase RF voltages result from the use of inherently symmetric and frequency-independent slot line tees, is described. Measurements of the fundamental and hamonic response of this amplifier, which uses an unpackaged, two-cell FET chip and exhibits the well known fourfold impedance advantage over parallel operation, are reported.

Patent
Adel A. A. Ahmed1
26 Sep 1977
TL;DR: In this paper, the principal conduction paths of first and second transistors connecting the input and output terminals respectively of the current amplifier to its common terminal, with a direct-coupled feedback connection between the input terminal and an interconnection of the control electrodes of the 1 and 2 transistors, are provided with capability for selectively providing or not providing current gain between their inputs and outputs.
Abstract: A current amplifier of the type having the principal conduction paths of first and second transistors connecting the input and output terminals respectively of the current amplifier to its common terminal, with a direct-coupled feedback connection between the input terminal and an interconnection of the control electrodes of the first and second transistors, is provided with capability for selectively providing or not providing current gain between its input and output terminals. To this end, a third transistor of complementary conductivity type has its principal conduction path included in the direct coupled feedback connection, being arranged to have its control electrode selectively clamped to the common terminal of the current amplifier to cause the current amplifier to exhibit current gain between its input and output terminals.