Showing papers on "FET amplifier published in 1984"

Capacitively Coupled Traveling-Wave Power Amplifier

Abstract: A new circuit concept which significantly improves the power-handling capability of a traveling-wave amplifier by coupling the active devices to the input gate line through discrete series capacitors is described. The approach is applied to a 1-W, 2-8-GHz monolithic amplifier design.

Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics

Abstract: A procedure has been developed for producing accurate and unique small-signal equivalent circuit models for carrier-mounted GaAs FET's. The procedure utilizes zero drain-source bias S parmeter tests to determine accurate values of carrier parasitics, and dc measurements to evaluate the FET's gate, source, and drain resistances. Subsequent S-parameter measurements at full bias are then used to resolve the FET into an equivalent circuit model that has only 8 unknown elements out of a possible 16. A technique for evaluating the frequency range of accurate data is presented and the FET model shown is useful well above the maximum frequency of measurement. Examples of device diagnostics are presented for RCA flip-chip mounted GaAs FET's.

Variable gain power amplifier

Abstract: A power amplifier having plural parallel amplification circuits of different gains selectively actuable to zero and maximum gains, and electronic switches to select a circuit for connection to a common output junction.

Design of Broad-Band Power GaAs FET Amplifiers

Abstract: A model is presented for the drain-gate breakdown phenomenon of GaAs FET's, based on experimental results. this breakdown model is added to a previously published large-signal model and incorporated in a powerful computer-aided design program called LSFET. The program is capable of searching for the optimum power load for an FET and simulating the power performance of multistage amplifiers. The design of power amplifiers is discussed in detail, using the knowledge gained from LSFET. Data is presented from a fabricated monolithic broad-band power amplifier chip showing good agreement between measured results and simulated curves.

A Particle Velocity Microphone for the Song of Small Insects and other Acoustic Measurements

Abstract: Conventional particle velocity microphones (see Olson, 1957) are not readily available, are expensive, fragile and large, so they are not commonly used in biological research, though their use in one situation where the source is highly reactive, the recording of Drosophila song, is now standard practice. Here, the particle velocity produced by the fly is far louder than the sound pressure, so high quality recordings can be made with minimal sound insulation (see Bennet-Clark, 1971; Bennet-Clark, Leroy & Tsacas, 1980). The microphones can also be used to localize sources of echoes and to measure other reactive conditions. The present design was developed as an alternative to the fragile aluminum-ribbon microphones used previously (Bennet-Clark, 1973) and has the advantages of low cost, small size, robustness and a broad frequency response. The transducer is an electret membrane open on both sides to the sound wave. The resonant frequency of the electret unit is at the top of the practical frequency range of the microphone (16—17 kHz). Below this, the output is proportional to the driving force, the pressure gradient, so rises 6dB per octave and leads by 90 in phase compared with the particle velocity (see Michelsen & Nocke, 1974). The microphone has three major components, a pressure gradient transducer, an FET impedance converter in the microphone head and an integrating amplifier to correct the frequency and phase response of the transducer. The electret unit is Radio Shack type 270-090 (Fig. 1) (Tandy Corporation; products are available world-wide). Retain the metal-coated electret membrane on its supporting ring; the 40/im thick plastic spacer washer, the perforated fixed electrode and the FET (see Fig. 1). The membrane is reassembled so as to be open to the sound wave on both sides. Dimensions of a brass housing and PTFE or Delrin (Acetal) insulator are shown in Fig. 2A. Assembly is shown in Fig. 2B. The electret and fixed electrode are separated by the 40 /xm spacer washer and the fixed electrode is separated from the housing by the insulator. The edges of the brass housing can then be crimped over to secure the components in position. If the electret is heated, it may discharge. The FET amplifier should be built close to the transducer. A suitable layout, which incorporates the 1 • 1 k£2 FET load resistor, is shown in Fig. 2C and the circuit diagram is shown in Fig. 3. In this layout, response varies as the cosine of the angle from the

Proposed vertical-type amorphous-silicon field-effect transistors

Abstract: Novel amorphous-silicon field-effect transistors (a-Si FET's) with a vertical channel have been proposed and demonstrated for the first time. The channel length of the new FET's is not limited by the photoetching process and thus can be reduced a great deal. Prototype FET's with a channel length of 1 µm had an on-off current ratio of more than 104and the on-resistance was proportional to the channel length, so far as it was longer than 1 µm.

Integrating capacitively coupled transimpedance amplifier

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.

Modeling of in Nonlinear Distortion GaAs MESFETs

Abstract: A modified harmonic balance approach is applied to a GaAs FET model to simulate two-tone intermodulation distortion and multiple siqnal suppression in MESFET amplifiers and mixers. Experimental results of a single stage FET amplifier are presented.

Optical fibre receiver

Abstract: An optical receiver, for use with optical fibre or for receiving a beam in free space, has its detector device, usually a PIN diode (D) connected in series with a resistor (R1) and to the base of a gallium arsenide field effect transistor (FET). Although the latter is satisfactory at most frequencies of operation, in certain load conditions, instability can occur at Gigahertz frequencies. To overcome this, the source-drain path of the FET is shunted by 50 ohm resistor (R2) in series with a capacitor (C) of about 5 nanofarads. In addition the FET is coupled to a bipolar transistor amplifier by a relatively long wire bond (L) which acts as an inductive impedance at the frequencies at which this instability occurs. These measures between them suppress this instability.

0.5 W 2-21 GHz monolithic GaAs distributed amplifier

Abstract: A novel circuit concept to reduce the gate loss using series capacitors on the gate feeding lines has been implemented for a distributed amplifier design. It has significantly increased the gate width of the amplifier with a resultant increase of the broadband output power and efficiency. A monolithic GaAs distributed amplifier using 6 x 300-micron FETs has achieved a record output power of 0.5 W over the 2 to 21 GHz frequency band with at least 4 dB gain. The power-added efficiency was 14 percent. The linear gain was 5 plus or minus 1 dB over the same frequency band.

Transimpedance amplifier with overload protection

Abstract: The front end of an optical receiver circuit (10) is of the type having a field-effect device transimpedance amplifier (16,21) which receives at its input (14) the photocurrent of a photodiode (12). A field-effect device shunt impedance (26) to protect against amplifier overloading is connected between the input and ground through a decoupling capacitor (28). The shunt (26) is controlled by a controller (30), which has its input connected to the output (24) of the amplifier (16) and its output connected to the gate of the shunt (26). The controller (30) compares the output (24) of the amplifier (16) to a threshold reference voltage for determining whether to activate the shunt (26) and regulates the gate voltage of the shunt (26) by means of an AGC amplifier. A direct current feedback resistor (32) is connected between the output (24) of the amplifier (16) and the source of the shunt (26). This prevents the d.c. component of large photocurrents from significantly changing the input bias voltage level of the amplifier (16).

Feed-forward microwave power amplifier with difference signal distortion cancellation circuit

Abstract: A feed forward microwave power amplifier having a divider for dividing an input signal into two parts, a first main amplifier for amplifying one of the divided signals, means for providing a part of the output of the first amplifier as a signal S 1 , means for providing a signal S 2 by another output of the divider, a subtractor for providing the difference between S 2 and S 1 , a second amplifier having the same gain as that of the first amplifier for amplifying this difference, a 3 dB coupler for coupling an output S 4 of the first amplifier and an output S 4 e, where e is a constant, of the second amplifier to provide coupled power which is free from distortion, and adjusting means for adjusting the level of signals S 1 and S 2 so that S 2 is higher than S 1 , and the value e is in the range between 0.2 and 0.5. The particular features of the present invention, compared with a prior feed forward amplifier, are the use of a 3 dB coupler, and the configuration of the second amplifier which accepts not only the distortion component but also some desired component of the output of the first amplifier.

CMOS sense amplifier with level shifter

Abstract: A common mode gain enhancing CMOS differential sense amplifier for a static RAM memory, straddled by level shifting circuits during the respective differential inputs to the sense amplifier.

Electro-acoustic converter with compensated frequency response characteristic

Abstract: A device for converting an electric signal into an acoustic signal, which comprises an electro-acoustic transducer unit (2) having a quality factor (Q) less than unity. The device further comprises an amplifier circuit (3) for driving the transducer unit. The amplifier circuit has a frequency-dependent gain characteristic (6) which increases towards the lower frequencies, starting from f 2 , in a frequency range between a first and a second frequency (f 1 and f 2 ), f 1 being the resonant frequency of the transducer unit (2) and f 2 being greater than f 1 . The efficiency can be increased if amplifier the circuit includes a special amplifier such as a switched amplifier, for example, a class-D amplifier, or an amplifier with a power supply that provides a DC voltage that depends on the drive level of the amplifier.

Complementary type MOS field-effect transistor circuit provided with a gate protection structure of small time constant

Abstract: A complementary type MOS field effect transistor circuit includes an input terminal, a P-MOS FET, an N-MOS FET connected in series with the P-MOS FET, a first resistor connected between the input terminal and the gate of the P-MOS FET, a second resistor connected between the input terminal and the gate of the N-MOS FET, a first diode connected between the gate of the P-MOS FET and a high voltage power supply terminal and a second diode connected between the gate of the N-MOS FET and a low voltage power supply terminal. The gate protection circuit of the circuit has a first part of the first resistor and the second diode and a second part of the second resistor and the second diode.

CMOS sense amplifier with N-channel sensing

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the 1-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.

Photodetector integrated circuit

Abstract: An integrated circuit incorporates a PIN diode connected to the gate of an FET. The semiconductor layers used to construct the diode are also the layers used to construct the FET, and provide a relatively low capacitance per unit area for the diode compared with that of the gate of the FET.

GaAs Dual-Gate FET for Operation Up to K-Band

Abstract: A high-frequency equivalent circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented in this paper. It is found that the gain of a dual-gate FET is higher than that of a single-gate FET at low frequency, but it decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable gain amplifier applications up to K-band has been developed. At 10 GHz, a I.2-mm gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic gain control range of up to 45 dB was obtained with an insertion phase change of no more than +-2 degrees for the first 10 dB of gain control.

High voltage, high frequency amplifier circuit

Abstract: High voltage, high frequency amplifier employing power transistors. The amplifier provides parallel ac signal amplification paths through each transistor and a single dc power path through the transistors in series. In one embodiment two FET's have their gate electrodes connected to an input terminal and their drain electrodes connected to an output terminal so as to provide two parallel ac amplifying paths while blocking dc current flow. The drain electrode of the first FET is connected through an RF choke to a source of dc operating potential, and its source electrode is connected through an RF choke to the drain electrode of the second FET. The source electrode of the second FET is connected to ground through a zener diode. A single dc conductive path is thus provided between the source of operating potential and ground through the two FET's in series.

Static memory having load polysilicon resistors formed over driver FET drains

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.

MOS FET amplifier output stage

Abstract: An output circuit particularly adapted for use in a pulse width modulation amplifier having a significantly reduced power loss during switching times. Inductors are coupled in series with the signal channels of two push-pull connected switching elements. High-speed diodes are coupled in parallel with the series combinations of switching elements and inductors.

A 6-GHz 80-W GaAs FET Amplifier with a TM-Mode Cavity Power Combiner

Abstract: A novel 8-way divider/combiner using TM/sub 010/- and TM/sub 020/ -mode cavities was developed. This divider/combiner has an insertion loss of 0.2 dB and a bandwidth of 600 MHz in the 6-GHz communications band. For broadening the operating bandwidth of the divider/combiner, two techniques of double cavities and tight coupling are described. Degradation of power-combining efficiency is also discussed when input signals into a power combiner have variations in amplitude and phase. By using this divider/combiner, an experimental 6-GHz 80-W GaAs FET amplifier with a combining efficiency of 85 percent was demonstrated to investigate the feasibility of a solid-state high-power amplifier.

A K-Band GaAs FET Amplifier with 8.2-W Output Power

Abstract: An 8.2-W GaAs FET amplifier with 38.6+-0.5-dB gain over a 17.7-19.1 GHz frequency band has been developed. This amplifier combines the outputs of eight multistage amplifier modules utilizing a radial combiner. This state-of-the-art power level has been achieved with AM/PM of less than 2°/dB. The third-order intermodulation products at 1-dB gain compression were 20 dBc, and variation in group delay over the frequency band was less than +-0.25 ns. Tests show that the amplifier is unconditionally stable and follows the graceful degradation principle.

Sense amplifier for CMOS semiconductor memory devices having symmetrically balanced layout

Abstract: A sense amplifier circuit for a CMOS DRAM or the like uses cross-coupled P-channel load transistors and cross-coupled N-channel driver transistors. Both of the P-channel transistors are in an N-well in the center of a symmetrical layout on the chip. Each N-channel transistor is split into two separate transistors, one on each side of the N-well, so that a balanced configuration is possible.

Linear FET power amplifier

Abstract: The present invention relates to an FET power amplifier whose transfer characteristics are parabolic or have a pronounced parabolic region. The amplifier is capable of linear operation due to a drain electrode bias network which includes a pair of serially connected quarter-wave transmission line sections connected at one end thereof to the drain electrode, and the interconnection point of the two quarter-wave transmission line sections is connected to both (a) a bias supply which causes the FET to operate over at least a portion of the parabolic region and (b) to a means which prevents envelope-induced drain bias voltage variations and presents a short-circuit to the drain terminal at a second harmonic of the input signal.

High frequency differential amplifier with adjustable damping factor

Abstract: A high-frequency differential amplifier is provided with a pair of buffer input stages, each having transistors the transconductance of which may be varied by varying a current source connected thereto. Since transistor frequency response and step response are dependent upon transconductance, bandwidth and damping factor of the step response may be varied for optimum performance without degrading gain and dynamic range characteristic of the differential amplifier. One useful application of the differential amplifier of the present invention is as an error amplifier in a cascomp amplifier circuit, such that the apparent damping factor of the step response of the cascomp circuit may be adjusted.

Dirt insensitive optical paper path sensor

Abstract: The present invention is concerned with a self-adjusting document sensor compensating for degradation of the sensor system. A suitable light source and a detector are provided, the output of the detector being fed into an amplifier whose gain depends upon a feedback signal. Periodically, the output of the amplifier is compared to a reference. If the output of the amplifier falls below the reference, a pulse is sent to a ripple counter whose digital output is fed back to the amplifier to change the gain of the amplifier. If the detector is an unbiased photodiode operating in the transconductance mode, the leakage currents and their subsequent effect on output with amplifier gain changes will be minimized.

A 2—18-GHz monolithic distributed amplifier using dual-gate GaAs FET's

Abstract: This paper describes a 2-18-GHz monolithic distributed amplifier with over 6-dB gain, ± 0.5-dB gain flatness, and less than 2.0:1 VSWR. Measured noise figure is below 7.5 dB, and power output capability is greater than 17 dBm, The amplifier is designed with dual-gate GaAs FET's instead of single-gate FET's for maximum gain over the design bandwidth. Cascaded amplifier performance will also be presented.

Gated transmission line model structure for characterization of field-effect transistors

Abstract: The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET's. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels. Further, the GTLM structure may be implemented in any existing semiconductor FET technology, including silicon, GaAs, and modulation-doped structures.

Semiconductor memory having charge transfer device voltage amplifier

Abstract: In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.