Showing papers on "FET amplifier published in 1985"

A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers

Abstract: A nonlinear equivalent circuit model for the GaAs FET has been developed based upon the small-signal device model and separate current measurements, including drain-gate avalanche current data. The harmonic-balance technique is used to develop the FET RF load-pull characteristics in an amplifier configuration under large-signal operation. Computed and experimental load-pull results show good agreement.

Computer Calculation of Large-Signal GaAs FET Amplifier Characteristics

Abstract: A simple and efficient method of GaAs FET amplifier analysis is presented. The FET is represented by its circuit-type nonlinear dynamic model taking into account the device's main nonlinear effects including gate-drain voltage breakdown. An identification procedure for extraction of the model parameters is described in detail and examples are given. The calculation of the amplifier response to a single-input harmonic signal is performed using the piecewise harmonic balance technique. As this technique is rather time-consuming in its original form, the optimization routine used to solve the network equations was replaced by the Newton-Raphson algorithm. Characteristics calculated with the use of the proposed method are compared with experimental data taken for a microwave amplifier using a 2SK273 GaAs FET unit. Good agreement at 9.5 GHz over wide ranges of bias voltage and input power levels are observed.

Transmit/receive switch

Abstract: A transceiver transmit/receive (T/R) switching arrangement for electrically decoupling the transceiver's receiver circuit from first and second transceiver ports during transmission, and for electrically decoupling the transceiver's transmitter circuit from the first and second transceiver ports during reception Each such circuit includes an amplifier for amplifying an applied microwave signal and operating with a relatively high output impedance when power is applied thereto Each amplifier is inhibited from amplifying an applied microwave signal when power is removed therefrom First bias means switchably applies power to the transmitter amplifier during transmission and removes power from the transmitter amplifier during reception to switch the relatively high output impedance of such amplifier to a relatively low output impedance Second bias means switchably applies power to the receiver amplifier during reception and removes power from the receiver amplifier during transmission to switch the relatively high output impedance of such amplifier to a relatively low output impedance Additional circuitry in the transmitter circuit couples the amplified microwave signal from the transmitter amplifier to the second transceiver port during transmission, and transforms the relatively low output impedance of the transmitter amplifier to a relatively high impedance at the second transceiver port during reception Similar circuitry in the receiver circuit couples the amplified microwave signal from the receiver amplifier to the first transceiver port during reception, and transforms the relatively low output impedance of the receiver amplifier to a relatively high impedance at the first transceiver port during transmission

Amplifier for integrated laser/FLIR rangefinder

Abstract: An integrated laser/FLIR rangefinder has a laser energy detector generating an electrical signal in response to impinging laser energy, a preamplifier for amplifying the signal and a post amplifier for selectively shaping the signal output of the preamplifier. The preamplifier has a plurality of transistors connected in parallel provided for substantially reducing noise, a summing circuit sums the outputs of the plurality of transistors, and a trans-resistance amplifier produces a low impedance voltage difference output. The post amplifier includes a delay line and an operational amplifier having a positive terminal and a negative terminal. The positive terminal of the operational amplifier and a first end of the delay line are connected to the trans-resistance amplifier for delaying the output of the trans-resistance amplifier. A second end of the delay line is connected to the negative terminal of the operational amplifier. The operational amplifier combines the delayed and undelayed output of the trans-resistance amplifier and produces a spiked-type difference voltage signal. A low noise frequency compensation circuit allows detectors with what is normally considered inadequate bandwidth to be used to detect the laser return pulses and still produce a reasonably fast pulse with a low noise-level suitable for rangefinding.

A Wide-Band Transconductance Amplifier for Current Calibrations

Abstract: A wide-band transconductance amplifier for current calibrations is described. The amplifier will deliver a ground-referenced constant current of 5 A rms from dc to over 100 kHz. Its stable magnitude and phase permit it to be used in precise power calibration systems to provide the current component of a phantom power source. The amplifier also provides a ground-referenced voltage output of 1 V/A for monitoring the magnitude and phase of the output current.

High-Voltage FET Amplifiers for Satellite and Phased-Array Applications

Abstract: The high-voltage FET amplifier (HVFA) configuration for power amplifier applications in satellite communications and phased-array systems can offer substantial improvement in DC-to-RF conversion efficiency. A proof-of-concept experiment, design considerations, and the RF results of MIC implementation at C- and X-band are reported. An X-band MMIC HVFA design is also presented.

Dual-gate, field-effect transistor low noise amplifier

Abstract: A monolithic low noise variable gain amplifier with series feedback includes a dual gate field effect transistor (DGFET) having a common source FET and a common gate FET with scaled gate widths and/or an interelectrode matching element connected to ground through a capacitor positioned between the two gates for reducing the minimum noise figure of the common gate FET and establishing the output load for the common source FET, and an inductive series feedback line for connecting the common source FET to ground. The amount of series feedback between the source and ground of the DGFET as well as the appropriate output load obtained through gate width scaling are selected to make the conjugate input impedance equal to the optimum impedance for a simultaneous noise match and power match.

Input protection device for integrated circuits

Abstract: A device (16) for preventing an input signal (VI) applied to a terminal (12) of an integrated circuit from damaging a section (18) of the circuit contains a regular enhancement-mode insulated-gate FET (Q1 or Q2), a resistor (R1 or R2) that enables the regular FET to act temporarily like a "floating-gate" FET, and a thick-oxide insulated-gate FET (Q3).

Bandwidth controlled data amplifier

Abstract: A transimpedance amplifier for data signals from a high impedance source includes a forward voltage amplifier and a feedback resistance. The feedback includes an FET. The resistance of the FET is controlled by a control signal derived from the data signal at the output of the transimpedance amplifier by a differentiator which generates pulses for each data transition and an average detector which generates a control signal responsive to the number of transitions per unit time, which is the data rate. The resistance of the FET is high when the data rate is low, reducing the noise magnitude and decreasing the noise bandwidth. When the data rate increases, the resistance of the FET decreases, providing greater bandwidth for handling the signal. The change in gain caused by the bandwidth control tends to change the magnitude of the output data signal. This may be corrected by an AGC loop which controls the open loop gain of the voltage amplifier. In order to reduce the effect of differences in the bit transition time, a limiter may be coupled to the bandwidth control signal generator.

FET output drive circuit with parasitic transistor inhibition

Abstract: A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads. The circuit thus sacrifices low output impedance for high input impedance and voltage swing during light output loading when output impedance is not very important, and sacrifices high voltage swing for high input impedance and low output impedance at heavy loads at which the impedance levels are more important than voltage swing.

Distributed amplifier using dual-gate GaAs FET's

Abstract: A 2-18 gigahertz monolithic distributed amplifier using dual-gate gallium arsenide field effect transistors for maximum gain over the design bandwidth.

ECL to FET interface circuit for field effect transistor arrays

Abstract: An interface circuit for coupling bipolar ECL logic circuit signals to an FET logic array. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar ECL logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.

Analog multiplier with improved linearity

Abstract: An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal. Separate current sources also supply the standing base currents for the transistors of one of the amplifiers, thereby correcting for static imbalances in the base drive circuitry.

X-Band Low-Noise GaAs Monolithic Frequency Converter (Short Paper)

Abstract: An X-band, low-noise GaAs monolithic frequency converter has been developed. Multicircuit functions, such as amplification, filtering, and mixing, were integrated on to a single GaAs frequency converter chip. The frequency converter consists of an X-band three-stage low-noise amplifier, an image rejection filter, an X-band dual-gate FET mixer, and an IF-band buffer amplifier. To minimize circuit size without degrading performances, an RC-coupled buffer amplifier was connected directly after a dual-gate FET mixer IF port, and one-section parallel and series microstrip lines were adopted for the amplifier. One-half-micron (1/2 µm) single-gate FET's and a one-micron (1 µm) dual-gate FET, which have an ion-implanted closely-spaced electrode structure, were used. Either via hole grounds or bonding wire grounds are selectable for the frequency converter. Chip size is 3.4x1.5 mm. The frequency converter provides less than 3-dB noise figure and more than 34-dB conversion gain.

Subranging analog-to-digital converter with FET isolation circuit between subtraction node and LSB encoder

Abstract: A 12 bit, 10 megahertz subranging analog-to-digital converter feeds a sampled analog input signal forward, without delay or attenuation, to a summing node. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sampled analog signal to produce a residue signal. A MOSFET isolation switch coupled between the summing node and the input of a high speed amplifier isolates the amplifier until the residue signal is stable, to prevent overdriving of the amplifier. A positive error voltage is added to the reference voltage inputs of the MSB flash encoder to enable use of a digital error correcting circuit that does not need to operate on negative binary numbers. A novel sample and hold circuit includes a closed loop operational amplifier that isolates the sampling capacitor and provides low output impedance to drive the MSB flash encoder and the summing node, provides low, stable, input offset voltage and very high bandwidth. The operational amplifier includes N-channel FET source followers coupled by balanced bias and level shifting circuitry to an NPN differential amplifer stage. Symmetrical, buffered cross-coupling form each of the source follower FETs to the opposite level shifting circuitry increases the amplification thereof and results in low DC offset voltage, high input impedance, and high gain and bandwidth.

On-line serial communication interface from a computer to a current loop

Abstract: An on-line serial communication interface is established from a digital circuit such as a computer or hand held terminal, to a current loop which has lines for connecting a transmitter to a power supply. The interface includes a diode which is connected in series with one of the lines of the current loop. The diode is connected in parallel to the source and drain of a FET. The control gate of the FET is connected to the output of a differential amplifier who receives as one of its inputs, a digital voltage pulse signal from the digital circuit. The other input of the amplifier is held at a selected voltage so that voltage pulses are output from the amplifier when the digital circuit generates its voltage pulses. This turns the FET on and off in synchronism with the voltage pulses, thus cutting the diode in and out of series with the line of the current loop. With the FET in its non-conducting off condition, the diode has a small voltage drop thereacross. This does not effect the current on the current loop. With the FET conducting and in its on state, the diode is cut out and its voltage drop is applied to the transmitter which is connected to the current loop. Communication can thus be established with the transmitter while again avoiding any interruption in the current on the current loop.

Subscriber line circuit having improved AC impedance matching

Abstract: An improved AC impedance matching arrangement including a first amplifier connected to a subscriber loop through the tip and ring conductors of a subscriber line circuit. The first amplifier is arranged to supply loop current to the subscriber loop through first and second resistors. Each resistor having a set DC value. A second amplifier connected to the tip and ring conductors is arranged to develop and output a signal responsive to AC signals applied to the tip and ring conductors from the subscriber loop. A feedback circuit connected to the second amplifier is arranged to receive the second amplifier output signal and develop and output to the first amplifier an impedance matching signal. The impedance matching signal raises the impedance seen by the tip and ring conductors above the set DC value of the first and second resistors.

High speed CMOS current sense amplifier

Abstract: A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines in the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).

Flux-Flow-Type Josephson Linear Amplifier with Large Gain and Wide Linear Range

Abstract: A linear amplifier using a flux-flow phenomenon in a long Josephson junction has been designed and tested by connecting a load resistance. The present experiment has demonstrated that a current gain of 500/Ws (1/µm) is obtained for the load resistance of 9 mΩ when an input signal is applied with a control line of width Ws (µm). An equivalent circuit of the amplifier has also been presented, which shows that the device is most suitable for current amplification with large gain in low impedance circuits.

High gain, low drift operational amplifier for sample and hold circuit

Abstract: A sample and hold circuit includes a high gain, low drift closed loop operational amplifier that isolates the sampling capacitor and provides low output impedance, and a low, stable, input offset voltage and very high bandwidth. The operational amplifier includes N-channel FET source followers coupled by balanced bias and level shifting circuitry to an NPN differential amplifier stage. Symmetrical, buffered cross-coupling from each of the source follower FETs to the opposite level shifting circuitry increases the amplification thereof and results in low DC offset voltage, high input impedance, and high gain and bandwidth.

Monolithic GaAs Dual-Gate FET Variable Power Amplifier Module

Abstract: The design, fabrication, and microwave performance of a monolithic four-stage GaAs dual-gate FET amplifier are described. A linear gain of 23 dB with 250 mW output power has been measured at 18 GHz. The highest power obtained was 500 mW with 21 dB gain at the same frequency. By varying the second gate bias voltage, a dynamic gain control range of more than 60 dB has been observed. The chip size is 6.45mm x 2.1mm x 0.1mm.

An fet switch for high frequency signals

Abstract: A solid state switching network inlcudes three FET switches arranged in a substantially "T" (or inverted "T") configuration. The network is controlled so that in an "OFF" or non-conducting state two of the FET switches are "OFF" and one is on. The high "OFF" impedance of the two FETs work against the low "ON" impedance of the third FET to provide an open circuit between the input and output of the switching network. The open circuit has greater isolation than is feasible with conventional circuits. The switching network or module is used in several configurations to couple data terminal equipment (DTE) to a communications highway.

A Low-Noise GaAs Monolithic Broad-Band Amplifier Using a Drain Current Saving Technique (Short Paper)

Abstract: A low-noise and low-power GaAs monolithic broad-band amplifier is proposed and has been developed, which has a new cascade connection with a large gate-width input FET and the other circuits in such a way that the output stage current flows through the input FET. The fabricated amplifier operates on +5-V single supply voltage, and provides a 3.3-dB noise figure, less than 180-mW power dissipation, and a 10-MHz--2.0-GHz bandwidth with 16-dB gain.

Antenna coupling amplifier and converter system

Abstract: An antenna coupling system includes separate low-noise receiving amplifier and down converter circuits for amplifying the antenna signal above background noise and for converting it down to frequencies compatible with a suitable receiver, respectively. The system is particularly intended for microwave frequency antennas of the type used to receive satellite signals. The amplifier circuit includes at least one microwave frequency amplifier, such as a GaAs FET, with a low frequency variable feedback circuit connected across it which is arranged to self-tune the amplifier to the antenna input signal strength. The converter circuit is of the image reject single conversion and image recovery type and is arranged to split the amplifier output signal into two parts which are each combined with a local oscillator signal and then re-combined in such a way that unwanted image signals are rejected.

Electromagnetically shielded narrow band electroencephalographic amplifier

Abstract: A low noise, high gain differential amplifier suitable for EEG amplification is constructed in a shielded metal enclosure, preferably on a ground plane circuit board. The amplifier is battery powered to eliminate all possibility of noise from the power system. The amplifier utilizes a pair of operational amplifiers to provide high input impedance for each of two input signals. A differential amplifier generates an internal signal which is filtered and amplified by a pair of bandpass amplifiers and overlapping low pass and high pass amplifiers.

Octave-bandwidth microwave FET doubler

Abstract: A microwave MESFET circuit which doubles the frequency of an input signal in the 4 to 8 GHz band is described. The circuit consists of a class C amplifier/phase-shifter combination followed by a single-stage band-reject amplifier. In the 8–16 GHz output band, an average conversion loss of 3 dB with fundamental rejection greater than 12 dB was achieved.

Differential pair amplifier enhancement circuit

Abstract: An enhanced differential pair amplifier circuit 28, 30 is described which provides a linearity correction technique. The linearity correction technique is designed to compensate for nonlinearities in the base-to-emitter output voltage of each transistor in a differential pair of transistors over the dynamic input range of the amplifier. The present invention comprises the inclusion of compensation diodes or transistors 42, 44 in the load circuit of each input transistor in the differential pair to compensate for nonlinearities.

Amplifier for high frequency signal

Abstract: In an amplifier for a high frequency signal used to amplify a signal having a high frequency in a television tuner, a receiver for satellite broadcasting, and the like, at least two stages of dc-coupled grounded-emitter type amplifiers (Q 1 , Q 2 ) are configured in an integrated circuit, a resistor (R 13 ) is connected between an emitter of the grounded-emitter amplifier (Q 2 ) in the second stage and the grounding, a terminal for connecting an external device is disposed to be connected via a bonding wire to the emitter of the grounded-emitter amplifier (Q 2 ) in the second stage, and a filter circuit (11) including an inductance of the bonding wire and developing a low impedance for a particular frequency is disposed between the terminal and the external grounding.

Monolithic series feedback low noise fet amplifiers

Abstract: A monolithic low noise amplifier is provided having at least one stage. Said stage including a Field Effect Transistor (FET) and an inductive series feedback element comprising a transmission line having an end connected to the FET source and an end connected to ground. A load matching network is attached to the FET drain to provide simultaneous noise match and power match.

Broadband HEMT and GaAs FET Amplifiers for 18 - 26.5 GHz

Abstract: Two types of broadband amplifiers operating over 18 to 26.5 GHz have been developed by using newly developed 0.4-µm gate HEMTs and conventional 0.25-µm gate GaAs FETs. The four-stage EEMT amplifier exhibits a noise figure of <= 7.2 d.B and a gain of 19.3 +- 1.8 dB and the five-stage GaAs FET amplifier exhibits a noise figure of <= 12 dB and a gain of 22.7 +- 2.2 dB over 18 to 26.5 GHz. The minimum noise figures in the measured frequency ranqe are 5.0 dB and 7.5 dB for the HEMT and GaAs FET amplifiers, respectively. No essential difference is found between the amplifiers in input/output VSWR, output power and temperature variation of noise figure and gain.