Showing papers on "FET amplifier published in 1986"

FET power converter with reduced switching loss

Abstract: A DC to DC power converter having reduced switching loss for operation at high frequencies. As disclosed, a buck, or forward, converter includes a first FET as the switching device in series with an inductor and a second FET as the flywheel device. At the common node to which the two FET's and the inductor are connected, there is sufficient capacitance that the FET's may be turned off without appreciable voltage change across the FET's. The value of the inductor is chosen, with respect to the input and output voltages and frequencies of operation involved, to insure that the inductor current polarity reverses each cycle, raising the node voltage to the level of the input voltage, substantially eliminating turn-on losses of the first FET. Control circuitry is provided for regulation of the power converter to control the peak-to-peak current in the inductor and to insure that at least a selected minimum value of the inductor current is present for each cycle of operation of the converter. An over-voltage protection circuit for the output of the converter is also provided.

Balanced dual-detector receiver for optical heterodyne communication at Gbit/s rates

Abstract: A balanced dual-detector receiver which requires low local-oscillator power has been designed and fabricated for optical heterodyne detection at 1·5 ?m wavelength and Gbit/s rates. The receiver consists of two InGaAs PIN photodiodes connected with opposite polarities to a high-impedance GaAs FET amplifier. Frequency response, noise suppression and noise spectrum measurements are reported.

A Nevv Method of Third-Order Intermodulation Reduction in Nonlinear Microwave Systems

Abstract: Third-order intermodulation distortion (IMD (3)) of some microwave systems has been analyzed using Vollterra series In this paper, theoretical results which have been calculated with a nonlinear FET model show that third-order intermodulation prodgcts of two input signals at f/sub 1/ and f/sub 2/ can be reduced by several orders of magnitude (in fact, theoretically, IMD (3) should be reduced to zero), with a low-frequency feedback at f/sub 1/- f/sub 2/, when the amplitude and the phase of this feedback are correctly chosen To verify this prediction, a circuit has been realized and measurements have been made on a one-stage FET amplifier First results confirm our analysis Experimental measurements show a 12-dB decrease of intermodulation products with our method

Gallium arsenide differential amplifier with closed loop bias stabilization

Abstract: A gallium arsenide differential amplifier is compensated against temperature and process induced variations so as to provide phase and amplitude matched differential output signals centered about an internal GaAs reference voltage. Compensation of the amplifier is effected by one or more current sources which are adjustably responsive to the dynamic common mode level of the output signals. The resultant amplifier provides a high common mode rejection ratio and facilitates implementation of otherwise impracticable differential GaAs circuit topologies.

GaAs voltage reference generator

Abstract: In a GaAs integrated circuit, a voltage reference generator includes a pair of Schottky diodes and a first, current-source connected, depletion-mode MESFET coupled in series to conduct current from a ground node to a voltage supply node. The current-source connected FET causes a constant current to flow from the ground node through the diodes, producing a constant voltage drop which generates a constant reference voltage at a reference node between the diodes and FET. A second pair of Schottky diodes is connected in series between the source of the FET and the voltage supply node, in a loop coupling the source to the gate of the FET, to provide a voltage difference Vgs across the FET proportional to voltage drop across the second pair of diodes. This voltage difference varies with fabrication process and temperature variations and causes the first FET to modify the amount of current flow to compensate so as to maintain a constant voltage drop across the first pair of diodes. A second FET is connected between the reference node and the first, current-source connected FET and has its gate coupled to the source of the first FET, either directly or through one of the second pair of diodes. Any variations in supply voltage are transmitted to the drain of the first FET to maintain a constant voltage Vds and current Ids, thereby stabilizing the reference voltage against supply voltage variations and noise.

System for maintaining low bit error rate in a starcoupled network of direct coupled stations

Abstract: A data process system has a plurality of stations or terminals linked to a star coupler over cables comprising separate sending and receiving transmission lines, the cable shield being connected to system ground. To minimize bit error rate when a station is powered down, the transmitting differential amplifier at each terminal station is connected between a bias voltage and a virtual ground created by a pair of diodes connected in parallel, their anodes being connected to a voltage source through a current limiting resistor, the cathode of one diode being connected to system ground, the cathode of the other diode being connected to one side of the transmitting amplifier to define the virtual ground. To further enhance noise rejection, a balanced differential network is connected to the outputs of a transistor pair at the amplifier output to the differential wire transmission line. The network comprises a resistor and diode connected in series between each transistor's emitter output and the amplifier bias voltage source, the combined resistance and dynamic impedance of each portion of the balanced differential network being equal. At the receiver end of the star coupler cabinet, a series resistor network is coupled from a bias voltage source for a differential receiver amplifier to the system ground. The receiver amplifier has two input transistors; the resistor network includes a resistor coupled across the transistor inputs of a resistance matched to the characteristic impedance of the cable; two additional resistors are connected in series between the ends of this resistor and the inputs to the amplifier transistors to define a relatively high offset voltage across the input to the receiver amplifier.

Distributed amplifier using Josephson vortex flow transistors

Abstract: A wide‐band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz.

Direct coupled FET logic using a photodiode for biasing or level-shifting

Abstract: A direct coupled FET logic (DCFL) circuit element has an active FET with source connected to a low reference voltage and drain connected through a pull-up FET to a higher reference voltage. An input is applied to the gate of the active FET and the output is taken from its drain, the pull-up FET having its gate connected to its source. In depletion mode configuration, a photodiode is connected to the gate of the active FET, the photodiode energizable to downwardly shift the gate voltage. In enhancement mode configuration, a photodiode is connected between source and gate of the pull-up transistor and is energized to shift the gate voltage upwardly. The photodiodes are integrated with the active and pull-up FETs and are energized by light or decay radiation.

Switched capacitor summing amplifier

Abstract: A switch capacitor summing amplifier is disclosed having a coupling means to couple desired signals to the active amplifier in response to an enable signal. The coupling is performed in synchronism to the "odd" phase of the sampling signals thereby improving noise, transient and DC offset performance while minimizing switch impedance sensitivity.

FET gate current limiter circuits

Abstract: A GaAs logic circuit uses a first FET to control the application of a logic signal from an input to an output. The first FET inherently has parasitic gate-to-source and gate-to-drain diodes. A control signal applied to the gate of the first FET controls the application of the logic signal to the output through the first FET. For a first FET that is an enhancement mode GaAs device, the gate current tends to forward bias such diodes under all operating conditions and tends to significantly increase the gate current. For a first FET that is a depletion-mode device, adverse operating temperatures can cause such tendency to forward bias these diodes and other circuit diodes. A limiter FET connected to the gate to limit the gate current and thus limits the forward biasing of the parasitic and circuit diodes. This reduces the effect on the gate current of variations in the power supplies to the FET, process variations and operating temperature variations. Limiting the gate current also limits the voltage drop resulting from the source resistance of the first FET, maintaining the voltage swing of the logic signal at the output at desired levels. If the gate current were not limited, the resulting greater forward bias of those diodes would cause an increase in the current drain from a voltage supply that biases the first FET. The unlimited forward bias would also result in a greater voltage drop from drain-to-source across the first FET, reducing the V OL at the output and resulting in lower noise margin.

Balanced differential amplifier

Abstract: In a balanced differential amplifier, a constant current source MOS FET operable in an unsaturated region is usually incorporated. When noise is inputted to the differential amplifier, the current source FET undergoes an influence of noise level superposed upon the input signal DC voltage thereof, thus deteriorating the constant current characteristics. To overcome this problem, a pair of current source MOS FETs are additionally incorporated therewith. Since the two current source MOS FETs operate near a boundary between saturated and unsaturated regions and further the gate voltages applied thereto varies in out-of-phase relationship to each other in response to input signal fluctuations, it is possible to keep constant the sum total of two currents flowing through the two constant current MOS FETs, thus improving the overall constant current characteristics and therefore the suppression capability against noise inputted in phase to the amplifier.

Wideband 1.5μm optical receiver using travelling-wave laser amplifier

Abstract: A high-sensitivity, wideband optical receiver using a travelling-wave laser amplifier in conjunction with a PIN photodiode and commercial 50Ω amplifier is described. A sensitivity of -37 dBm at 1 Gbit/s has been achieved, with a 17dB net amplifier gain.

Drive circuit with limited signal transition rate for RFI reduction

Abstract: An amplifier applies turn-on bias to the gate electrode of an output field-effect transistor in response to a first level of an input signal applied to the amplifier. A switched power source supplies operating current to the amplifier for developing the turn-on bias when the amplifier input signal is at the first level. A feedback-controlled bypass circuit diverts a portion of the operating current from the amplifier during an initial turn-on period and gradually reduces the magnitude of the diverted operating current as the output transistor turns on thereby producing a "soft" turn-on of the output transistor so as to minimize a potential for creating radio frequency interference in nearby RFI sensitive devices such as the tuner in a television or radio receiver. Complementary circuits include dual current supply and diversion circuits providing controlled rise and fall times for complementary field-effect output transistors.

A 12-dB High-Gain Monolithic Distributed Amplifier

Abstract: By reducing gate and drain line loss associated with the active elements of a distributed amplifier, significant gain improvements are possible. Loss reduction is achieved in a novel monolithic distributed amplifier by replacing the common-source FET's of the conventional design with cascode elements having a gate length of one-quarter micron. A record gain of over 10 dB from 2 to 18 GHz and a noise figure of 4 dB at 7 GHz have been achieved on a working amplifier. Details of the design and fabrication process are described.

Sense amplifier circuit for semiconductor memory device

Abstract: A sense amplifier circuit for use in an MOS memory device, including bipolar sensing transistor, MOS load transistors connected to respective of the bipolar sensing transistors, and a constant current source, whereby high switching speed and high sensitivity are achieved.

An 11-GHz GaAs frequency divider using source-coupled FET Logic

Abstract: A GaAs one-fourth frequency divider is fabricated to evaluate the ultrahigh-speed performance of source-coupled FET logic (SCFL) having normally-on FET's with small negative V th values. High-transconductance (240 ms/mm) 1/2-µm gate-length FET's and an air-bridge interconnection line technology are successfully developed. A maximum toggle frequency F max of 11 GHz is achieved with a power dissipation of 149 mW. Furthermore, 9.7-GHz F max with low power dissipation of 52 mW was also obtained.

Quasi auto-zero circuit for sampling amplifiers

Abstract: A sampling amplifier (22) consisting of a series combination of a signal input terminal (12), a first capacitor (C1), a first amplifier (A1), a second capacitor (C2), a second amplifier (A2), and a signal output terminal (VOUT2) is able to sample at a higher frequency by providing a low impedance path between the signal output terminal (VOUT2) and a junction (VOUT1) between the first amplifier (A1) and the second capacitor (C2) to quasi auto-zero the amplifier between samples.

Overdrive control of FET power amplifier

Abstract: An overdrive control for a GaAs FET power amplifier is provided by a PIN diode attenuator positioned at the input of the FET amplifier where the amount of attenuation is controlled by a control signal derived from the gate current of the following FET amplifier.

44-GHz monolithic GaAs FET amplifier

Abstract: Millimeter-wave monolithic GaAs FET amplifiers have been developed These amplifiers were fabricated using FET's with MBE-grown active layers and electron-beam defined sub-half-micrometer gates Source groundings are provided through very low inductance via holes The single-stage amplifier has achieved over a 10-dB gain at 44 GHz A 300-µm gate-width amplifier has achieved an output power of 60 mW with a power density of 02 W per millimeter of gate width

Two stage push-pull MOSFET power amplifier

Abstract: A power amplifier includes an output stage comprising a pair of complementary MOSFET power transistors connected in push-pull fashion between the positive and negative poles of a split DC power supply, with the sources of the transistors connected together to ground. The input stage includes another pair of complementary MOSFET driver transistors having their gates connected together to the input signal. The drain signal of each of the driver transistors is resistor coupled to the gate of one of the power transistors, and biased so that the driver turns off as the power transistors turns on. The amplifier output signal is taken between the common point of the split DC power supply and ground.

GaAs-Monolithic IC's for an X-Band PLL-Stabilized Local Source

Abstract: X-band GaAs-monolithic voltage controlled-oscillator (VCO), divide-by-four analog frequency divider, and Wilkinson power splitter have been developed for frequency stabilization of an X-band Iocal source in a phase-locked loop (PLL) system.The VCO has a series feedback configuration and utilizes an optimized design procedure to yield the highest dc-RF efficiency ever reported for a GaAs-monolithic FET oscillator. The frequency divider has a novel structure which applies a dual-gate FET mixer and two RC-coupled FET amplifier stages to establish a closed loop for generating a 1/4 subharmonic component of an input frequency. The Wilkinson power splitter consists of an isolation resistor and two quarter-wavelength lines, which have been realized in both meander and spiral forms. A VCO-driven frequency divider system incorporating these IC's consumes 380-mW total power to provide the 1/4 subharmonic component of the VCO frequency with more than 3-dBm output power over a 10.86-- 11.01-GHz range.

Circuits to provide desired conductance characteristics using a FET

Abstract: The drain-source conductance of a wide variety of FETs can be made to conform to a predetermined function of a control signal. The control signal is multiplied by a factor and an offset is added or subtracted therefrom to derive a modified control signal. The modified control signal is then applied to the gate of a FET. The factor and the offset are such that the drain-source conductance of the transistor is substantially the predetermined function of the control signal. When a desired attenuator characteristic defined with respect to a FET is to be provided using a FET having characteristics different from those of the reference FET, the control signal to the FET used can be similarly modified so that the desired attenuator characteristics are obtained. A dual path compressor or expander employing an attenuator (which includes a FET) in its further path can be made to conform to a desired compression or expansion characteristic defined with respect to a similar arrangement and with respect to a reference FET conductance control characteristic. This can be accomplished by making the conductance control characteristics of the FET to be used to conform to the desired conductance control characteristic.

Buffered FET logic gate using depletion-mode MESFET's.

Abstract: A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (VI); and thereby a high load drivability with a low power consumption rate is realized.

Feedback amplifier compensation circuitry

Abstract: A frequency-compensated transistor feedback amplifier provides relatively wide bandwidth and relatively large phase and gain margins, irrespective of the transconductance of the transistors in the amplifier. Each one of three preferred embodiments (10, 50, 104) of the invention includes a transconductance stage (20, 68, 68) and an amplifier stage (12 and 14, 54, 54 and 14). The transconductance stage delivers an input signal to the amplifier stage, which produces an amplified replica of the input signal. A feedback capacitor (24, 88, 24 and 88) connected between the output and the input of the amplifier stage provides dominant pole compensation by which the magnitude of the loop gain diminishes by 6 dB/octave with increasing frequency. The capacitor provides a forward feedthrough path for any residual portion of the input signal so that the residual portion arrives at the output of the amplifier stage in substantially the same phase relation with that of the output signal of intermediate frequency. This invention can be implemented in circuitry whose input signal is taken from a transconductance stage that comprises an amplifier configured in either a single-ended output mode or a double-ended output mode.

High speed operational amplifier

Abstract: A high speed low power linear two micron CMOS operation amplifier comprises an input differential amplifier stage having feedback current mirror loads connected to a four vertically stacked transistor cascode output stage. Current domain operation of the amplifier enable fast operation through current mirror arrangements internal to the amplifier. Pass transistors of the cascode stage are dynamically biased providing the amplifier with single gain stage reducing the need for large compensation capacitors while improving the dynamic range of the output signal. The gain of amplifier is ninety decibels with a unit gain frequency bandwidth of fifty megahertz and with low power dissipation at two milliwatts.

Low noise signal detection for a charge transfer device by quadrature phasing of information and reset noise signals

Abstract: Charge transfer devices typically include a periodically reset floating element output stage coupled to an FET amplifier for sensing the transferred charges. For reducing both low-frequency l/f noise and high-frequency reset noise, the duty factor of the device clocking signals and the reset signal are picked so that at a selected multiple of the clock signal repetition rate, the information component is in phase quadrature with the reset noise component. The charge transfer device output signal is then synchronously detected with a reference signal which is in phase with the selected multiple of the information component.

Fully-differential operational amplifier for MOS integrated circuits

Abstract: A single-stage fully differential operational amplifier has a high open-loop gain and can be incorporated in a very small area of silicon and has a very small number of bias interconnection lines. The amplifier includes two identical arms each having similar bias and loads, transconductance and common-mode feedback elements. Each of the aforementioned three elements in each branch have the same current flowing therethrough when the amplifier is quiescent.

Dielectric resonator microwave oscillator having enhanced negative resistance

Abstract: A dielectric resonator microwave oscillator in which the gate of a FET is connected to a resonance circuit. An inductor is connected to the drain of the FET, and the output is taken from the source of the FET. This dielectric resonator microwave oscillator has enhanced negative resistance and positively starts the oscillation even when there is a low reflection coefficient of the resonance circuit. Using a circuit which consists of a capacitor and inductor between the source and the output terminal, a further increasing of negative resistance at the gate of the FET is obtained.

CMOS Current sense amplifiers

Abstract: A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines ih the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).

Cascaded internal impedance dependent amplifier with accurate variable gain control.

Abstract: An internal impedance dependent amplifier has a gain as determined by the impedance at a predetermined node within the amplifier. A PIN diode (42) is coupled to the predetermined node (26). The PIN diode (21) is driven with a forward biased current (Ip) which serves as the accurate gain control signal for the amplifier. In the preferred embodiment, the PIN diode (42) is driven by an operational amplifier (56) in such a manner that the impedance thus coupled to the predetermined node in the amplifier is temperature independent. Because the PIN diode has an impedance given by: log R = A + B log Ip, where R is the impedance of the PIN diode; Ip is the forward biasing current; and A and B constants which are different for each PIN diode, the voltage (Vc) applied to the operational amplifier (56) driving the PIN diode (42) is linear with respect to the impedance of the PIN diode (42) and hence the voltage gain of the impedance controlled amplifier to which the PIN diode is coupled. This characteristic of the gain of the amplifier allows the amplifier to be cascaded in series (A1 ... A11) and to preserve the same impedance relation as expressed above for the cascaded series of amplifiers as well. Thus, the gain in dB of the cascaded series of amplifiers is log linear with respect to a common control voltage applied to each of the amplifiers of the series.