Showing papers on "FET amplifier published in 1987"

Dynamic sense amplifier for CMOS static RAM

Abstract: A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier. The use of powerful transistors to produce differential output signals significantly reduces the amount of circuitry needed in the output driver of the memory device incorporating this sense amplifier. Furthermore, this sense amplifier significantly improves the access time of a memory device by enabling sensing with very small input signals from a memory cell, and by reducing the delay between sensing and providing an external data output signal.

Relationship between measured and intrinsic transconductances of FET's

Abstract: In exploratory study of FET's, such as the study of deep-submicrometer-channel FET's, carrier transport quantities are extracted from the measured transconductance of a FET. The extraction requires that the intrinsic transconductance of the device be calculated from the measured one, which is generally degraded by source and drain parasitic resistances. We have derived an equation that allows the calculation of the intrinsic transconductance of a FET from the measured transconductance, under the assumption that source and drain series resistances are independent of bias. The derivation does not assume zero drain conductance, nor does it involve any specific FET model. Therefore, the derived equation works in both saturation and linear regions of a FET, regardless of its channel length. The equation was tested by adding external resistors in series with source or drain of ultra-short-channel MOSFET's. Within the accuracy of the measurements, experimental results have proved that the equation is correct.

A differential switched-capacitor amplifier

Abstract: A monolithic realization of a switched-capacitor amplifier is reported. It has op-amp offset voltage cancellation without requiring the output to slew to ground each time the amplifier is reset. The amplifier is very insensitive to low op-amp gain. It also has clock-feedthrough cancellation. Finally, it can be used as a differential amplifier with both inputs being sampled at the same instance.

Dual gate FET mixing apparatus with feedback means

Abstract: When a dual gate FET is used in a mixing type circuit, the non-linear characteristics of an over-driven gate on the FET is used to create the sum and difference of the gate applied signals at the drain of the FET. Although feedback typically is used to increase the linearity of a class A amplifier where a single gate FET is used, the feedback in the present circuit overcomes the problem of maintaining a stable operating point for the mixer circuit while not interfering with the performance of the FET as a mixer. Thus, with the feedback to the first gate, the sensitivity of the DC bias on the second gate is decreased and can be set with simple (wide tolerance) components.

Composite power amplifier with redundancy

Abstract: A power combiner includes an input power splitter driving a plurality (N) of amplifiers. The amplifier outputs have Z0 output impedance and are coupled by transmission (TX) lines of Z0 characteristic impedance to the junction point of a lossless power combiner. Short-circuiting switches located λ/4 from the junction power disconnect failed amplifiers from the combiner. According to the invention, a number M

Integrated low-noise amplifiers in CMOS technology

Abstract: A review is given of the several noise sources of FET transistors. They allow to optimize the performance of a single FET with respect to low equivalent input noise and cutoff frequency as well. Several circuit implementations in CMOS technologies are discussed.

Sense amplifier circuit for semiconductor memory

Abstract: A sense amplifier circuit comprises a first amplifier circuit for detecting the data from a memory cell and generating an output signal in accordance with the detected data, a first load MOS transistor of one conductivity type connected between an output terminal of the first amplifier circuit and a power source terminal, a second amplifier circuit for detecting the data from a dummy cell and generating an output signal in accordance with the detected data, a second load MOS transistor of one conductivity type and a third load MOS transistor, which are connected in parallel between an output terminal of the second amplifier circuit and the power source terminal, and a comparator for comparing the output signals from the first and second amplifier circuits and generating an output signal in accordance with the result of the comparison. The third load MOS transistor is a MOS transistor of an opposite conductivity type whose back gate is connected to a reference potential terminal.

Programmable band-pass amplifier for use with implantable medical device

Abstract: A switched-capacitor, band-pass, programmable amplifier is used as a sense amplifier in an implantable cardiac pacemaker. Switching means are used to switchably connect various capacitors to the same amplifier circuits. Clock generator means are used to generate clock signals that are used to control the rate at which the switching means operates. By programmably selecting the switching rate to be a desired value, the band-pass characteristics and gain of the sense amplifier may be varied. When a pacemaker stimulation pulse occurs, the band-pass characteristics and/or gain of the sense amplifier, may also be automatically varied to improve amplifier recovery time. The rate at which the capacitors are switchably connected to the amplifier circuits, may be selected remotely, thereby allowing the band-pass characteristics to be programmable.

Switchable mode amplifier for wide dynamic range

Abstract: There is disclosed an amplifier device for use with a photodetector for amplifying wave energy signals received by the photodetector and converted into electrical signals. The amplifier device includes a first amplifier having its input connected to a junction between the photodetector and first and second photodetector load impedances. A negative feedback amplifier is connected to the output of the first amplifier. The negative feedback amplifier provides a feedback voltage to the first load impedance when in its first mode of operation and effectively reduces the voltage feedback to the first load impedance when in its second mode of operation. A switching device is provided to effectively switch the second load impedance in and out of circuit with the photodetector to effectively change the photodetector load impedance and alter the bias voltage to the feedback amplifier. As, a consequence, the feedback amplifier is able to operate in either of its first or second modes of operation respectively switching the amplifier device from a good sensitivity, broad bandwidth transimpedance amplifier to a follower amplifier of improved dynamic range.

Fast latching flip-flop

Abstract: A fast latching flip-flop has a transparent latch master section with an input amplifier, an output latch, a current source connected to provide current for the input amplifier and the output latch, and a switch for applying the current from the current source to either the input amplifier or the output latch. A slave section is connected to the output latch to transfer the data from the output latch to the output of the fast latching flip-flop. A delay transistor is inserted between the switch and the input amplifier to add delay in the turn-off of the input amplifier. Additional delay is attained by connecting a plurality of diode-connected transistors to the junction of the delay transistor and the switch. The result is a reduction of the metastable region between the turn-off of the input amplifier and the turn-on of the output latch.

MOS FET drive circuit providing protection against transient voltage breakdown

Abstract: A drive circuit suitable for producing a high voltage drive output signal has an output stage formed of a P-channel MOS FET (4) and an N-channel MOS FET (5) connected for push-pull operation. The circuit is configured such that even with a supply voltage applied to the output stage which is higher than the ON-state withstand voltage of the MOS FETs (4, 5), this value of voltage is prevented from being applied to a MOS FET (4, 5) which is in the ON state, i.e. by providing voltage-dropping resistors (R₁, R₂) connected between the drain electrodes of the MOS FETs (4, 5) or utilizin g a circuit which prevents each MOS FET (4, 5) from entering the ON state until after the other MOS FET (5, 4) has entered the OFF state.

MMIC (monolithic microwave integrated circuit) low noise amplifier

Abstract: The invention relates to a low noise amplifier for use at microwave frequencies which may be fabricated using integrated circuit techniques. In accordance with the invention, critical components are made adjustable so as to simplify the design process and manufacturability of the amplifier. A two stage low noise amplifier is disclosed in which TEE networks are used as input and output networks in each stage, and in which one element of each TEE includes an adjustable spiral inductor. The value of each adjustable spiral inductor may be adjusted by removal of one or more air bridges disposed along the inner turn of the inductor. This permits one to "tune" the amplifier and optimize its performance.

Low noise ultra high frequency amplifier having automatic gain control

Abstract: A radio frequency amplifier includes a bipolar and a field effect transistors (FET) which are cascoded for efficient operation and simultaneous gain control. Bias circuitry is connected to the control electrode of the FET to stabilize the output bias thereof. Negative feedback circuitry is connected between the output electrode of the FET and the control electrode of the bipolar transistor to stabilize the other bias levels within the circuitry. An AGC circuit is connected to the feedback circuitry to provide an automatic gain control function.

Semiconductor switching circuit

Abstract: of the Disclosure A semiconductor switching circuit comprises an output FET receiving a photovoltaic output generated by a diode array responsive to a light signal from a light emitting element, a depression mode driving FET connected at the drain and source to the gate and source of the output FET, and a constantvoltage conduction element connected in parallel with a resistor connected across the gate and source of the driving FET. The sensitivity of the circuit is elevated by setting the value of this resistor relatively high, whereas the high speed operation can be assured by having discharge current of an accumulated charge across the drain and gate of the output FET bypassed through the resistor.

A 2-20 GHz, High-Gain, Monolithic HEMT Distributed Amplifier

Abstract: A low-noise 2-20 GHz monolithic distributed amplifier utilizing 0.3-micron gate-length HEMT devices has achieved 11-dB +- 0.5 dB of gain. This represents the highest gain reported for a distributed amplifier using single FET gain cells. A record low noise figure of 3 dB was achieved mid-band (7-12 GHz). The circuit design utilizes five HEMT transistors of varying width with gates fabricated by E-beam lithography.

CMOS Precision voltage reference generator

Abstract: A differential voltage, set by threshold differences of a natural FET and an implanted FET, is amplified by a switched capacitor amplifier and filtered by a filtering circuit to provide an accurate reference voltage that is independent of temperature, process variation and power supply voltage changes.

Method of making self-aligned field-effect transistor

Abstract: A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

Vehicle power window control circuit with reverse battery protection

Abstract: A power window control circuit for a motor vehicle includes a FET and SCR in series across the power supply with their junction connected to one side of a motor armature, the other side of the motor armature being switchable between power supply terminals. To provide reverse battery protection, no anti-parallel diode is provided around the SCR. The activation circuit for the FET includes a capacitor bootstrap circuit controlled by a switching transistor and a zener diode from the drain to the gate. When conduction from the switch through the motor and SCR is stopped, the inductive energy from the armature windings dissipates through the internal anti-parallel diode of the FET. When opposite conduction from the FET through the motor and switch is stopped, the inductive energy causes the voltage across the FET to rise to the zener voltage and turn on the FET sufficiently to dissipate it.

High power diamond traveling wave amplifier

Abstract: An FET device especially useful in common gate amplifier circuits used as amplifiers of microwave and millimeter wave signals. The device has a diamond film layer constituting the device's channel. Device geometry is selected so that, in a common gate amplifier circuit, device input and output are impedance matched to avoid phase cancellation between input and output. In one embodiment a boron nitride layer is disposed heteroepitaxially with the diamond channel and separating the channel from the gate. In another embodiment plural such devices are yoked together integrally source to drain in such a manner that charge carriers entering the second and subsequent stages do so at maximum velocity without the need to accelerate from zero or low velocity. The resulting device has a higher power handling capacity, upper frequency range, and dynamic range.

FET transconductance amplifier with improved linearity and gain

Abstract: A FET high frequency analog amplifier circuit employs a feed-forward technique to provide a first order correction of amplifier distortion. In one embodiment, the amplifier is configured as a differential set of cascode FET stages (12A, 12B). A linearization stage (14) is connected across the output cascode transistors (22) to provide a cancellation signal to reduce amplifier nonlinearities. The linearizing circuit includes a pair of field effect transistors (32) in source-coupled arrangement with their respective bases driven by the drains of the differential amplifier input transistors (20). The gates are further driven by biasing current sources (36). The drains of the linearizing transistors are cross connected to the drains of the cascode output transistors, thereby injecting a compensating error signal into each differential output node and cancelling circuit nonlinearities. The amplifier is well suited for fabrication in integrated circuit form, especially using gallium arsenide technology.

SIS Mixer to HEMT Amplifier Optimum Coupling Network (Short Paper)

Abstract: The coupling network between a superconductor-insulator-superconductor (SIS) mixer and a high-electron-mobility-transistor (HEMT) amplifier is investigated from the point of view of minimizing the overall noise temperature and also increasing the saturation level of the mixer. The effect of a negative output impedance of the mixer upon the amplifier noise is considered and an optimum negative source resistance is found. The amplifier noise at this optimum negative source resistance is shown to be related to the noise wave coming out of the amplifier input terminals. Key words: SIS, HEMT, low-noise, negative resistance.

FET reference voltage generator which is impervious to input voltage fluctuations

Abstract: A reference d.c. voltage generator is disclosed which includes a series circuit for first and second field effect transistors or FETs. The first FET serves as a high-impedance constant current supply, while the second FET functions as a resistor for generating at its soure a reference d.c. voltage. A series circuit of two FETs is connected between the gate and source of the first FET to bias the first FET such that a current flowing therein is kept constant, whereby the gate-source voltage thereof can be stabilized even when the power supply voltage is fluctuated.

Method of making vertical field effect transistor with plurality of gate input cnnections

Abstract: A method of making a vertical field effect transistor (FET) having a plurality of gates which are isolated from each other. Each gate has a contact thereby enabling a single gate which is turned "on" to cause the vertical FET to conduct a current. This configuration allows for a logical "or" function to be implemented in a vertical FET.

Power Optimization of GaAs Implanted FET's Based on Large-Signal Modeling

Abstract: Large-signal models for ion-implanted, MMIC-compatible GaAs FET's are reported using different techniques. There are (i) S-parmneter meawrements, (ii) low-frequency capacitances combined with dc Z-V characteristics, and (iii) physical data. The results obtained with each model are compared to high-frequency power measurements, and the relative merits of each technique are discussed. The models permit investigation of the influence of frequency, implantation energy, doping density, drain bias, recess depth and gate length on the small- and Iarge-signal FET parameter and saturation mechanisms. FET's fabricated with these data give optimum gain and power characteristics at the desired frequency of operation.

Input compensation circuit for superbeta transistor amplifier

Abstract: An improved input current compensation circuit is provided for a dual branch amplifier, particularly an amplifier employing superbeta transistors. The compensation circuit has a superbeta compensation transistor which is matched with the superbeta amplifier transistors, a bipolar transistor connected across the superbeta transistor in a manner analogous to a voltage limiting circuit in the amplifier section, and current sources which provide operating currents to both the superbeta and bipolar compensation transistors. The base current of the superbeta compensation transistor is mirrored to the bases of the superbeta amplifier transistors, and the superbeta transistors, bipolar transistor and current sources in the compensation section are scaled relative to corresponding elements in the amplifier section so that the superbeta amplifier transistor base currents are substantially compensated by current mirrored from the compensation circuit. A negative feedback circuit is provided to keep the superbeta compensation transistor in its linear operating region, and current sources in the compensation section are selected to mitigate second-order errors.

Sense amplifier optimized lay-out from dynamic random access memories on complementary metal oxide semicondutor

Abstract: A sense amplifier having an optimized structural lay-out for D-RAM on the C-MOS provides the same time lag from nodes of the sense amplifier and does not produce unbalances in the voltages. This allows the sense amplifier to uniformly distribute the parasitic capacitance of the bit lines used for the D-RAM on the C-MOS. The sense amplifier is connected to a memory cell array so that transistors and capacitors are coupled with a plurality of bit lines and word lines situated on the semiconductor substrate. The amplifier has a first semiconductor region which is within an N type well region located on the P type semiconductor substrate to form a first latch circuit. A second semiconductor region which is contiguous to the N type well region is also formed on the semiconductor substrate to form an N-MOS transistor. Lastly, a third semiconductor region, which is contiguous to the N type well region and the second semiconductor region, forms a second latch circuit having an N-MOS transistor. Thus, the sense amplifier is formed at a gate of the N-MOS transistor so that a transfer from the gate of N-MOS transistor through openings in the substrate caused by voltage differences produced by the charge distribution and storage capacitor of bit lines during an active cycle does not have a time lag.

Wideband microwave matrix amplifier

Abstract: A microwave amplifier that both multiplicatively and additively amplifies microwave frequency signals. The amplifier, herein coined a matrix amplifier, is a distributed amplifier with two or more tiers (rows) of transistors. Each tier has a plurality of transistors which additively amplify the signal entering that row of the amplifier, and each row multiplicatively amplifies the output of the previous row. The gates of the transistors in each row are sequentially coupled to an input transmission line having a series of transmission elements. The outputs of all the transistors from each row are sequentially coupled to the input transmission line of the next tier, except that the outputs of the last tier are coupled to an output transmission line for transmitting the output of the amplifier to an output node. Furthermore, each transmission lines has (1) at least one line termination at one of its ends for absorbing signals incident on that end of the transmission line, and (2) biasing means for d.c. biasing the transmission line at a corresponding voltage potential.

Processing and Characterization of Ultra-Small Silicon Devices

Abstract: Processing, design, and characterization issues are discussed for advanced field-effect (FET) and bipolar transistors. Results are presented from work on N-channel FET's with gate lengths below 0.1 ?m, and on the role that polysilicon emitter contacts play in high current, high speed bipolar devices. For FET's over 750mS/mm transconductance was achieved at liquid nitrogen temperature operation. In the case of bipolar devices it was found that maximizing the gain enhancement derived from the polycrystalline/single-crystal interface without regard to resistive effects does not lead to the highest performance in submicron transistors. Based on previous experience and on our recent work, we believe that silicon technology faces no insurmountable obstacles as it progresses into the deeply submicron regime.

Constant current biased common gate differential sense amplifier

Abstract: A sense amplifier circuit for sensing signals present on data lines from a memory. The differential inputs are converted to single-ended outputs by two pairs of common gate differential input transistors and a pair of active loads. The single-ended outputs are amplified by a pair of drivers and the amplified outputs are presented as balanced differential outputs of the sense amplifier. A pair of current sourcing transistors provide DC biasing current to each of the pair of input transistors, wherein the current sourcing transistors are biased to operate in a saturation region, such that voltage changes on the data lines do not cause a change in the current source to prevent signal loss to the input transistors.

Schottky diode logic for e-mode fet/d-mode fet vlsi circuits

Abstract: A digital logic circuit using Schottky diodes as the nonlinear logic element, a single power supply and an E-mode MESFET as an inverter in the open drain configuration. Temperature compensation of the threshold voltage of the E-mode FET is provided. The circuit is particularly suited for use with a GaAs substrate.