Showing papers on "FET amplifier published in 1989"

CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range

Abstract: A CMOS complementary, self-biased, differential amplifier provides for a rail-to-rail common-mode input-voltage range of operation. A self-biasing scheme is used to provide negative feedback to the amplifier in order to assist in providing a common-mode rejection but providing high gain amplification for differential-mode amplification.

Attenuation compensation in distributed amplifier design

Abstract: A high-gain common-gate FET that presents at its drain a broadband impedance characterized by a (frequency-dependent) negative resistance and a capacitance is examined theoretically and experimentally. Loading the input and/or the output lines of a distributed amplifier with this circuit reduces the signal losses, leading to an increase in the allowed number of active devices with a consequent increase in the gain-bandwidth and gain-maximum-frequency products. The cascode circuit, a related loss reduction network, is also evaluated because of its use in distributed amplifiers. Several designs employing the common-gate FET loss-compensating circuit and/or the cascode amplifying circuit are compared to a conventional distributed amplifier optimized for gain-bandwidth product. Simulated gain-maximum-operating frequency product increases of 27% to 245% over that of the optimized conventional distributed amplifier are shown. The increase in single-stage amplifier gain provided by this technique often results in (proportionally) higher maximum output power. >

Planar broadband FET balun

Abstract: Three active FET baluns, using resonant, reactive and resistive/reactive compensation are disclosed suitable for monolithic implementation. A single balanced mixer configuration including a resistive/reactive active FET balun coupled with a pair of single ended FET mixers in a push pull configuration is disclosed which is also suitable for monolithic implementation.

Boost clock circuit for driving redundant wordlines and sample wordlines

Abstract: A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit are connected to the series pass FET transistors for enabling one or the other of the differnetially-connected FET transistors into conduction. The pair of capacitive coupling elements coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.

Class C-E high-efficiency tuned power amplifier

Abstract: A numerical analysis of a Class C-E tuned power amplifier is presented, along with a design procedure and experimental results. The efficiency and the maximum operating frequency of the amplifier are intermediate between those of the Class C and E amplifiers. The collector efficiency of the Class C amplifier is about 70%, whereas that of the Class E amplifier is about 96%. The maximum operating frequency of the optimum-efficiency Class E amplifier is, however, limited by the transistor output capacitance. The operating frequency of the Class C amplifier can be at least 16 times higher than that of the optimum-efficiency Class E amplifier at the same output power, DC supply voltage, and transistor output capacitance. The Class C, E, and C-E amplifiers can be obtained with the same circuit topology. The class of operation depends on the values of the load-network components. The tradeoff between the efficiency and the maximum operating frequency is evaluated for all three classes, using nonlinear time-domain simulation. The experimental and theoretical results are in good agreement. >

A low power low noise amplifier for a 128 channel detector read-out chip

Abstract: The design of a low-power, low-noise CMOS (complementary metal oxide semiconductor) amplifier is described. The amplifier was designed using the folded cascode configuration and was implemented on a 3- mu m double polysilicon process. The amplifier is part of a 128-channel charge amplifier array chip for use in the readout of radiation detectors with many channels. Aspects of the amplifier design such as bandwidth, pulse response, and noise are discussed, and the effects of individual transistors are shown, thereby relating circuit performance to process parameters. Circuit and radiation test results are included. The results show that a noise level as low as 670 electrons has been achieved with a risetime of 240 ns and a power density of less than 0.45 mW per channel. >

A new wide-band Darlington amplifier

Abstract: A wideband Darlington amplifier topology which is well suited for maximum-bandwidth, moderate-gain, matched-impedance applications is described. A test circuit using a silicon bipolar monolithic technology with an f/sub T/ of 9 GHz has been fabricated. Measured results show a 9.3 dB insertion gain and a 3.2 GHz bandwidth for the packaged device. >

Silicon bipolar fixed and variable gain amplifier MMICs for microwave and lightwave applications up to 6 GHz

Abstract: Three MMICs for microwave applications up to 6 GHz and for digital lightwave applications up to 5 Gb/s are presented. They are: (1) a 8-dB gain, 6-GHz half-power loss, fixed-gain wideband amplifier, fabricated in modified discrete transistor process: (2) a high-gain low-noise (1.6 dB) amplifier that can also be effectively used as a transimpedance amplifier; and (3) a 3-GHz variable-gain amplifier (VGA) with a wide gain control range (50 dB), suitable for 5 Gb/s-data rates in digital lightwave systems. The circuits were fabricated using a nonpolysilicon-emitter silicon bipolar process for transistors with a gain-bandwidth product f/sub T/=10 GHz and maximum oscillation frequency f/sub max/=20 GHz. >

Two-state, bilateral, single-pole, double-throw, half-bridge power-switching apparatus and power supply means for such electronic power switching apparatus.

Abstract: Two-state, bilateral, single-pole, double-throw, half-bridge power-switching apparatus capable of high speed, high current switching over a duty factor range of zero percent to 100% includes a single-wire connector to a source of switching signals, a first FET whose gate is connected to the single-wire connector, and a second FET having its gate connected to the drain of the first FET and its source connected to the drain of the first FET through a device for preventing, in part, cross-current from the first FET to the second FET and for permitting the gate voltage on the second FET to be raised sufficiently high to turn on the second FET. The apparatus also includes a system for delivering on/off signals to the second FET and for holding the second FET on or off in response to switching signals having a duty factor in the range of zero percent to 100%.

Integrated circuit for level shift

Abstract: An integrated circuit for level shift is a parallel-connected circuit comprised of a first circuit including a first MOS FET of one conductive type, a third MOS FET of another conductive type and a first MOS FET of the other conductive type which are series-connected in this order and a second circuit including a second MOS FET of the one conductive type, a fourth MOS FET of the other conductive type and a second MOS FET of the other conductive type which are series-connected in this order, wherein gates of the first and second MOS FETs of the one conductive type are connected respectively to the output side and input side of an inverter connected to a low voltage electric power source, gates of the third and fourth MOS FETs of the other conductive type both are connected to a reference voltage source, a gate of the first MOS FET of the other conductive type is connected to a common junction point of the fourth MOS FET and the second MOS FET of the other conductive type, a gate of the second MOS FET of the other conductive type is connected to a common junction point of the third MOS FET and the first MOS FET of the other conductive type, and the parallel-connected circuit is connected to a high voltage electric power source.

Large-swing CMOS buffer amplifier

Abstract: A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5- mu m CMOS technology. The prototype occupies an area of 275 mil/sup 2/. It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Omega with a total harmonic distortion of less than 0.025%. >

A high efficiency 835 MHz linear power amplifier for digital cellular telephony

Abstract: The authors describe an approach to linear power amplification for digital cellular telephony which exploits the high efficiency of a class-C amplifier. An average efficiency exceeding 50%, with third-order intermodulation products 30 dB down, has been demonstrated. Low cost, moderate complexity, conventional RF technology was used in the amplifier circuitry. A block diagram of the 835 MHz linear power amplifier is presented. >

Load driver with reduced dissipation under reverse-battery conditions

Abstract: A relay-less load driver circuit includes an FET that couples a battery to a load. A bias circuit that selectively turns the FET on during normal operation also turns the FET on in reverse-battery conditions to avoid high power dissipation by an intrinsic diode associated with the FET.

Motor drive circuit with reverse-battery protection

Abstract: A relay-less drive circuit for an inductive load preferably uses a transistor switch to couple the load to a battery, and provides a path for recirculating current around the load, which path includes a recirculating diode coupled in series with another transistor switch, such as an FET. the FET's drain and source terminals are connected to the recirculating diode, and the FET is biased, such that the FET is on when the battery is connected to the load with its nominal polarity, and the FET is off when the polarity of the battery is reversed.

Domino effect shunt voltage regulator

Abstract: A High Voltage Regulation apparatus which uses an amplifier having an arbitrarily large number of stacked MOSFETs to provide low impedance shunt regulation with a "domino effect". Voltages of many kilovolts can be conveniently regulated. voltage sharing among the devices is assured by the domino arrangement. External capacitances are added to optimize low impedance voltage regulation, including an external capacitor connected between the drain and gate of each stage to equalize the drain to gate and gate to source capacitances. There may also be an external capacitor connected between the drain and source of each stage to provide low amplifier impedance at high frequency, or a lumped external capacitor connected across the entire amplifier string, to provide low amplifier impedance at high frequency. The amplifier uses a unity-gain inverting amplifier as its basic building block. N-number of these building blocks are stacked to accommodate whatever voltage stand-off level is desired.

FET power performance prediction using a linearized device model

Abstract: An analytic model has been developed which, based on a linearized device model, describes the power output at 1-dB gain compression, optimum load impedance, and load-pull contours of a field-effect transistor (FET) explicitly in terms of device parameters. Applications of the model to practical devices including commercial metal-semiconductor FETs and a 0.25- mu m-gate modulation-doped FET showed agreement with measurements to 40 GHz. >

A novel 4-18 GHz monolithic matrix distributed amplifier

Abstract: The authors describe the design, fabrication, and performance of a 4-18 GHz matrix distributed amplifier which incorporates a novel biasing scheme enabling the amplifier to run at higher voltages while drawing only half of the current of conventional multistage amplifiers having comparable gain levels. A voltage divider is used at the input of the FET pair to derive the gate bias, ensuring that both FETs are biased at the same point. This scheme enables the stages to be connected in cascade at RF frequencies and in cascode for DC biasing, thus conserving current. The amplifier shows >13 dB gain across the frequency band using a chip area of only 1.9 mm*2.1 mm. >

Parallelled amplifier with switched isolation resistors

Abstract: A paralleled amplifier arrangement includes a plurality of amplifier modules, the output ports of which are coupled to a common combining node. Switches are coupled to the output ports for selectively decoupling one or more of the amplifier modules from the combining node during those intervals in which the amplifier modules are held in reserve or are nonfunctional. Each amplifier module is associated with an isolation resistor which is coupled to all the isolation resistors. In order to reduce losses attributable to the isolation resistors when the decoupling switches are operated, the isolation resistors are each coupled to a switched network which decouples the isolation resistors associated with the decoupled amplifier modules.

Bootstrap transimpedance amplifier: a new configuration

Abstract: In any photodetector application, capacitance is a major factor which limits response time. Decreasing load resistance improves this aspect, but at the expense of sensitivity. In the subsequent amplifier, positive feedback may be used with caution. It is possible to combine the effective stability of negative feedback with the desirable features of the positive type. An alternative approach, the bootstrap transimpedance amplifier, has been investigated. This offers the usual advantages of the transimpedance amplifier together with an effective capacitance reduction technique.

Method and resulting devices for compensating for process variables in a CMOS device driver circuit

Abstract: According to the present invention, an improved CMOS integrated circuit and an improved method of forming the circuit is provided. The circuit has a first FET device and a second FET device, and at least one performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related process variable condition. Each of said FET devices has an output signal at least one characteristic of which is changed by a change in the performance related variable condition. The first and second FET devices are connected such that the one output characteristic of the second FET device acts in opposition to the one output characteristic of the first FET device to provide a merged output signal representative of the combined effect of the two FET devices. The second FET device is constructed so as to be more responsive to the variations in said performance related variable condition than the first FET device and to have a weaker output signal than the first FET device, whereby the merged output signal of the two FET devices is maintained relatively constant irrespective of variations in the performance related variable condition.

Load current control-type logic circuit

Abstract: An inverter portion, which is to be basic logic circuit, includes switching FETs corresponding to input terminals and a load FET. A logic signal inputted into each of the input terminals drives each corresponding switching FET, thereby to output a prescribed logic signal from an output terminal. Further, a load for restricting a current flowing in the load FET is connected between the gate and the source of the load FET. In addition, a load current control FET is provided for controlling the current in this load. A gate potential of the load current control FET is produced by a diode OR circuit. The diode OR circuit outputs a logic OR of the logic signals inputted into the respective input terminals, and supplies it to the gate of the load current control FET as a load current control signal.

FET overtemperature protection circuit

Abstract: A first signal (V 1 ) related to FET drain to source voltage and a second signal (V 2 ) related to FET source current are compared and the FET (11) is turned off when the first signal exceeds the second signal by a predetermined amount. This corresponds to turning the FET off whe the drain to source on resistance of the FET exceeds a FET on resistance value corresponding to a maximum allowable FET die temperature. Thus the FET is turned off for excessive due temperatures to prevent damage to the FET. A start-up circuit (41, 42) is provided to insure proper initial turning on of the FET, and a short circuit protection circuit (30) is provided for turning the FET off it the source current exceeds some maximum current limit. Accurate, effective monitoring of the FET die temperature is provided without the use of an additional temperature sensing element provided adjacent the FET.

An improved buffer for bioelectric signals

Abstract: An AC-coupled amplifier that offers a high input impedance, thus making it suitable for bioelectric signal amplification, is discussed. The necessary formulas for calculating its input impedance and transfer function in order to facilitate its adaptation to different applications are presented. By using the appropriate equations, it is possible to choose the value of the output impedance, the maximum overshooting in the frequency response, and the low corner frequency. The effective input impedance is limited by common mode input capacitances associated not only with the operational amplifier, but also with input protections, RF filter, and circuit layout. These capacitances provide an increased impedance near frequency of resonance. >

Operational transconductance amplifier with improved current source capability

Abstract: A two-stage, operational transconductance amplifier is provided with a rail-to-rail output swing, zero systematic offset voltage and very low quiescent current, but with the ability to both source and sink substantially greater than the output stage quiescent current to a load during transients. The amplifier has found particular application as part of a switched capacitor gain and filtering block in an implantable defibrillator, but is widely applicable.

A very low‐noise FET input amplifier

Abstract: We describe the design, schematics, and performance of a very low‐noise FET cascode input amplifier. This amplifier has noise performance of less than 1.2 nV/(Hz)1/2 and 0.25 fA/(Hz)1/2 over the 500 Hz to 500 kHz frequency range. With modest changes it could be extended to a wide variety of uses requiring low‐noise gain in the 1 Hz to 30 MHz frequency range.

Low current enhancement mode MMICs for portable communication applications

Abstract: A successful application of GaAs enhancement mode MESFET technology has been demonstrated for a portable communication system. A description is given of a single-stage enhancement mode FET amplifier dissipating about 10 mW of power and achieving a gain of 10 dB with a return loss of 14 dB at 900 MHz. This completely monolithic amplifier was unconditionally stable inside and outside the frequency band. High- and low-temperature performance of the amplifier is also reported. The circuit was tested at 70 degrees C and at -20 degrees C to study the temperature dependence of the circuit. While no appreciable degradation was observed at 70 degrees C, a drop in gain of about 2 dB was noticed at -20 degrees C. >

Non-linear amplifier and non-linear emphasis/deemphasis circuit using the same

Abstract: A non-linear amplifier circuit comprises a low band eliminating filter for receiving an input signal from an input terminal, a logarithmic amplifier and an adder for adding the output signal of this logarithmic amplifier and the input signal with a predetermined polarity relationship to produce an output signal and sending this output signal to an output terminal. The logarithmic amplifier comprises an amplifier for receiving the output signal of the low band eliminating filter, a bidirectional logarithmic element and a resistor coupled in parallel thereto between the input and output terminals of the amplifier.

FET monolithic microwave integrated circuit variable slope gain-equalizer

Abstract: A MMIC variable slope gain-equalizer varies the conductance of depletion mode Schottky gate FETs to controllably insert frequency dependent resonant members in a modified bridged-T configuration. Resistors connected from circuit input port to output port define the arms of the "T" and a T-node to which a first frequency dependent resonant member is connected in series with a first FET. A second FET and a second frequency dependent resonant member are each connected in series between the circuit ports, bridging the T. Preferably a third frequency dependent resonant member is series connected with the second frequency dependent member. Each frequency dependent resonant member resonates at about the highest frequency of interest, typically about 18 GHz. When the first FET is on and the second FET off, maximum attenuation at lower frequencies is inserted into the circuit, and when the first FET is off and the second FET on, minimum attenuation is inserted at lower frequencies. Intermediate levels of FET conductivity produce intermediate levels of frequency dependent attenuation. In a first embodiment, FET conductivity is controlled by two push-pull control voltages. A second embodiment uses a single control voltage to vary conductivity. The first embodiment operates at about 0-18 GHz, while the second embodiment operates at about 2-18 GHz. Each embodiment realizes a variable slope gain-versus frequency temperature function of between about -0.6 dB/GHz to about +0.2 dB/GHz with a 0 to +3VDC control voltage change.

Apparatus and method for combining output signals from parallelly coupled power field effect transistors in high frequency amplifiers

Abstract: Apparatus and method for parallel operation of radio frequency transistor amplifier circuits in a Class D mode of operation at radio frequency signal ranges without the use of frequency limiting components is disclosed. A driver circuit provides the input signals for each radio frequency transistor amplifier circuit. A transformer is disclosed that combines the output signals of the radio frequency transistor amplifier circuits while matching the amplifier circuit impedance and the transformer load impedance (i.e., the antenna impedance). The transformer eliminates the need for DC blocking capacitors between the primary and secondary windings of the transformer. The transformer/power combiner includes a plurality of (1:1) transformer units having the unit input terminals (power amplifier output signals) coupled in parallel and having unit output terminals coupled in series. The parallel/series configuration permits impedance matching of the power amplifier output impedance and impedance driven by the transformer. The primary structure of the unit transformer is metal sleeve surrounded by a ferrite core. The secondary winding includes at least one conductor cable inserted through the metal sleeve. The metal sleeve is coupled between the power amplifier output terminal and the DC power source.

Amplifier circuit using feedback load

Abstract: An amplifier circuit of this invention includes a first-stage amplifier, an amplifier element connected to the output terminal of the first-stage amplifier as a feedback load, and a further amplifier element connected between the output and input terminals of the amplifier element, and performs negative feedback through a load of the first-stage amplifier. As the amplifier element, a transistor is used, and as the further amplifier element, an emitter-follower transistor is used.