Showing papers on "FET amplifier published in 1991"

A high-speed clamped bit-line current-mode sense amplifier

Abstract: A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling. >

Impedance-matched, class F high-frequency amplifier

Abstract: An impedance matched class-F high frequency amplifier includes an input matching circuit receiving high frequency signals connected to the gate of the FET. The drain of the FET is connected to an output matching circuit which matches the fundamental frequency and the second harmonic frequency, and the output of the output matching circuit is connected to an even harmonic terminating circuit. The stray reactance componance at the output impedance of the FET is offset by the output matching circuit, and therefore the even harmonics terminating circuit can more accurately terminate the second harmonic frequencies.

Dual mode power amplifier for radiotelephone

Abstract: A dual mode power amplifier operable in etiher the linear mode or the saturation mode. The power amplifier, when comprising a portion of a radio transmitter, permits efficient amplification of either a frequency modulated or a composite modulated signal by operation of the amplifier in the saturation mode or the linear mode, respectively. A processor determines the modulation-type of the signal and generates a signal to cause operation of the amplifier in either the saturation mode or the linear mode.

Power amplifier for broad band operation at frequencies above one ghz and at decade watt power levels

Abstract: An octave band decade watt power amplifier is disclosed using compact and efficient MMIC fabrication techniques. The power amplifier is a two stage amplifier in which the driver transistor has two cells, and the power transistor has four cells, with each power cell double the size of the driver cells. Both transistors are of an optimized topology facilitating efficient broad band operation at matchable impedance levels. They are interconnected by three four section impedance matching networks of which the input network is coupled to a 50 ohm signal input terminal. The input and the interstage network are both formed on the same substrate as the transistors. The output network is formed on a separate substrate having a high dielectric constant (i.e. 37) which facilitates efficient and compact matching of four power transistor cells to a single output terminal for connection to a load at the conventional (50 ohm) impedance.

Multi-stage optical amplifier

Abstract: This invention relates to an Erbium-doped fiber amplifier having multiple stages of amplification for providing enhanced performance. More specifically, optical means is located intermediate first and second stages of doped optical amplifying fibers adapted to receive a pump signal at a pump wavelength where the optical means is adapted to modify the net gain characteristics of the multi-stage amplifier. Presently, all known Erbium-doped fiber amplifiers utilize relatively simple single stage amplifiers which support required ancillary optically passive components such as isolators, filters, pump multiplexers, power monitors and the like at either end of the amplifier. This requirement of having the passive optical element at an end of thhe optical amplifier not only lends to relatively stringent design and fabrication tolerances for a high performance optical amplifier, but it restricts the design of the Erbium-doped fiber amplifier to an embodiment which prevents exploitation of the various unique properties of the Erbium-doped fiber amplifier.

Dynamically biased amplifier

Abstract: An amplifier (102) which can be dynamically biased is disclosed. A controller (118) determines when to change the bias to the amplifier (102), in order to achieve low frequency splatter. This is accomplished by changing the bias level of amplifier (102) between a substantially linear (class A) mode of operation, and a substantially nonlinear (class B) mode of operation. During the critical periods when the amplifier (102) is being turned into and out of operation, the amplifier (102) is placed in a substantially linear mode of operation, thereby reducing the output harmonics which develop. In another aspect of the invention a radio (300) which employs a dynamically biased amplifier (102) is disclosed.

Two-mode oscillator

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

MOS array multiplier cell

Abstract: A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.

Resonant loop resistive FET mixer

Abstract: A mixer includes a local oscillator (LO) matching network having an LO input port, an RF matching network also having an input port and an IF filter which provides an IF output from the mixer. A FET having a gate, drain and source operates at the center of the mixer. A resonant loop is connected between the drain and gate of the FET. The gate of the FET is connected to an output of the LO matching network. The drain of the FET is connected to an output of the RF matching network. The source of the FET is connected to an input of the IF filter. The resonant loop may incorporate a DC blocking capacitor which does not function as part of the resonant loop, but which serves to block DC allowing the drain and gate of the FET to be biased independently.

Wide-dynamic-range amplifier with a charge-pump load and energizing circuit

Abstract: An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected. The output (collector) of the differential amplifier is connected to the gate of the NMOS driver transistor so that the load current through the driver transistor is held regulated to a value proportional to the input or reference voltage that is applied to the other input of the differential amplifier. The peak pulse voltage of each charge pump is greater than the DC supply voltage from which the driver transistor and the two charge pumps are energized so that the dynamic range of both the input control voltage and the amplifier output to the gate of the NMOS driver transistor is much greater than the DC supply voltage to the integrated circuit.

Driven-common electronic amplifier

Abstract: Sampled input, common mode driven, differential amplifier. Both inputs to a differential amplifier are sampled with a high input impedance amplifier. These signals are then summed and used to drive a buffer amplifier. The output of the buffer amplifier then drives the floating common node of a floating power supply. The floating power supply powers the main differential amplifier.

Wideband integrated distortion equalizer

Abstract: For use in a spacecraft for correcting amplifier distortion, a wideband distortion corrector avoids the need for directional couplers. The corrector includes a FET mounted in a miniature microwave-type housing. Signal flows through the source-to-drain channel. A gate impedance selected to be inductive at the operating frequency is coupled from the FET gate to the platform of the package, and may be simply a loop of bond wire. The channel connects by a strip transmission line to an amplifier, the distortion of which is to be corrected. For enhanced bandwidth, an inductor is coupled between the FET source and drain electrodes within the miniature housing. The platform of the package is coupled to the reference conductor of the transmission line. In one embodiment, direct bias voltage is applied by way of a bias tee across a strip transmission line and ground, and galvanic connections cause the bias to appear between the FET gate electrode and the channel.

RF amplifier assembly

Abstract: A series resonant circuit (17, 16, 22, 21, 19) is employed to minimize the area utilized to form an RF amplifier (10). The series resonant circuit (17, 16, 22, 21, 19) utilizes a capacitor (21) along with inductors (17, 19, 22) that are formed by bonding wires (17, 19, 22) which interconnect the components of the amplifier (10). The series resonant circuit is tuned to the second harmonic of the fundamental frequency applied to the RF amplifier (10). The area consumed by the series resonant circuit (17, 16, 22, 21, 19) is small thereby minimizing the amplifier's size.

Semiconductor relay circuit

Abstract: A semiconductor relay circuit includes a MOS FET (14) receiving a photovoltaic output generated across a photovoltaic diode array (13) responsive to a light signal from a light-emitting element (12), across gate and source electrodes (15,15a) of which MOS FET a control circuit (16) is connected to be at a high impedance state during the generation of the photovoltaic output but to be at a low impedance state upon disappearance of the output, and resistors (17,18) are inserted in series respectively in each of a path flowing a current from the photovoltaic diode array across the gate and source electrodes of the MOS FET and a path flowing a discharge current from a capacity across the gate and source electrodes of the MOS FET to the control circuit, whereby the setting of rise and fall of circuit output signals can be made easier.

High speed fully differential operational amplifier

Abstract: An operational amplifier operates with a higher bandwidth by doubling the gate drive to an output stage transistor without increasing the gain of an intermediate stage amplifier. The increased gate drive allows the output stage transistor to be reduced in size while providing the same output drive level to the capacitive load. The smaller output stage transistors reduces its gate capacitance for providing stable operation with the increased bandwidth.

One GHZ CATV repeater station

Abstract: An apparatus for and a method of RF amplification of signals up to 1 GHz. The apparatus, known as a repeater station, is for use in Community Antenna TeleVision transmission (CATV). The RF amplification (gain) stage includes two multitransistor distributed amplifier stages connected in a push-pull configuration. Each distributed amplifier includes four transistors connected to produce two-each cascode circuits. The distributed amplifier stages are operated in push-pull configuration by means of a 180° phase shifting power splitter. The push-pull configuration of the distributed amplifier operates in combination with the 180° phase shifting power splitter to cancel the 2IM distortion created within the distributed amplifiers, and to double the output capability of a single distributed amplifier. By installing very linear cascode connected transistors in the distributed amplifier, CATV operators can effectively double the basic circuit output capability and at the same time maximize RF bandwidth achievable with a given transistor.

Harmonic injection amplifier

Abstract: An amplifier having band pass filters and resonators for injecting, mixing and downconverting, i.e., recycling, second and third harmonics to increase the amplifier's efficiency. Various aspects of amplifier design are developed for enhancing efficiency.

A Josephson junction to FET high speed line driver made of TlCaBaCuO

Abstract: A Tl-Ca-Ba-Cu-O superconducting flux flow transistor (SFFT) was used as an active impedance converter between Josephson and FET circuitry. The input of the flux flow device is a control line of low impedance that can be driven by a tunnel junction. The output is the signal across the SFFT which is made of a parallel array of weak links. The output impedance is typically greater than 5 Omega , with a maximum voltage swing of over 100 mV into a 50- Omega system. The switching of an all-Nb junction induced a 90-mV voltage swing at the FET input and over 200 mV at the FET output. The line driver can operate anywhere between 4.2 K and 85 K with minor changes in speed (+or-5 ps) and output level (+or-10 mV). The switching time measured was about 100 ps and was fixture limited.

Track-and-regenerate amplifiers and memories using such amplifiers

Abstract: An amplifier of the present invention is suitable for use as sense amplifier in memories. Some embodiments of the amplifier are simple, fast and consume little power. A memory using the amplifier is also provided.

A CMOS readout amplifier for instrumentation applications

Abstract: An integrated readout amplifier for instrumentation applications in smart sensor systems is presented. A fully integrated CMOS version of such an amplifier has been developed using switched-capacitor techniques. The amplifier system provides differential input capability, programmable amplification, clock generation, and low-pass filtering on the chip. The output signal is continuous in time and the system can be used without any of the special precautions necessary for sampled-data circuits. Emphasis was put on high PSRR (-63 dB at DC), low noise (10- mu V/sub rms/ input equivalent wideband noise) and offset, low harmonic distortion, and small amplification error ( >

A CMOS wideband amplifier with 800 MHz gain-bandwidth

Abstract: A fully differential unity-gain stable CMOS wideband operational amplifier, realized in a standard 1.2- mu m CMOS process, is presented. The amplifier uses a capacitive feedforward technique to avoid p-channel transistors in the signal path. With a well-considered transistor sizing, the parasitic poles of the amplifier are shifted to the highest possible frequencies that can be reached with this 1.2- mu m technology. In this way, a gain-bandwidth product of 800 MHz and a phase margin of 53 degrees can be obtained. >

A cooled 1-2 GHz balanced HEMT amplifier

Abstract: The design details and measurement results for a cooled 1-GHz-bandwidth L-band high electron mobility transistor (HEMT) amplifier are presented. No facilities-were available for measuring low-temperature S parameters, but the HEMT noise parameters were measured at a physical temperature of 12 K. The absence of S-parameter information precluded the design of a feedback amplifier, so a balanced configuration was adopted. This has the advantage of providing a good input match even though the amplifiers in the two arms of the balanced circuit are poorly matched. However, there are disadvantages. The loss of the input hybrid degrades the noise temperature and coupling errors in the hybrids, and differences between the amplifiers reduce the gain and result in a noise contribution from the input load. In the amplifier described, these effects degrade the noise temperature by less than 1 K. The amplifier uses commercially available packaged HEMT devices. At a physical temperature of 12 K the amplifier achieves noise temperatures between 3 and 6 K over the 1 to 2 GHz band. The associated gain is approximately 20 dB. >

Symmetrical differential amplifier circuit

Abstract: An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions. Furthermore, an offset voltage caused in each amplifier circuit is canceled out by connecting two sets of symmetrical-type amplifier circuits.

High gain limiting erbium-doped fiber amplifier with wide dynamic range

Abstract: An optical limiting amplifier is disclosed having a high gain over a wide dynamic range of input power levels. The amplifier has an input stage (102) and an output stage (103), each of which includes an erbium-doped fiber amplifier (104, 106). The erbium-doped fiber amplifier in the input stage provides a high gain in order to saturate the amplifier in the second stage. The erbium-doped fiber amplifier in the output stage is fabricated with a small core diameter to saturate at reasonably small signal levels, and has a relatively lower total number of erbium ions in order to limit amplification once deep saturation is reached.

Cmos band gap reference circuit

Abstract: A band gap reference circuit configuration includes first and second bipolar transistors having base-to-emitter voltages. An emitter resistor is connected to the first bipolar transistor. An operational amplifier is connected to the bipolar transistors for processing a difference generated between the base-to-emitter voltages of the first and second bipolar transistors to generate a largely temperature-independent reference voltage. The bipolar transistors are parasitic transistors, and the operational amplifier is constructed in MOS technology.

DC to 10-GHz mixer and amplifier GaAs IC's for coherent optical heterodyne receiver

Abstract: The authors describe a number of design techniques that are effective for enhancing sensitivity and bandwidth. A Gilbert-cell circuit with a single-to-balance conversion input buffer and a peaking circuit are adopted for the mixer. In addition, a wideband amplifier is proposed that adopts a novel multiple-feedback cascode FET amplifier configuration with an LC input matching network. Finally, a novel interconnection technique is proposed that improves impedance matching between ICs and the package over a wide frequency range up to 10 GHz. These ICs were fabricated using a 0.2- mu m gate self-aligned GaAs MESFET process. These techniques could enable a highly sensitive multigigabit-per-second coherent optical heterodyne receiver to be implemented. >

Amplifier with actively clamped load

Abstract: An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems.

Adaptive amplifier circuit

Abstract: To allow a universal replacement telephone handset, an adaptive amplifier circuit uses DC power available from a host telephone set base to discriminate between low resistance and high resistance base power supplies. It emulates either a carbon microphone or an electret microphone, whichever is appropriate for the set base. The circuit couples a microphone (10) and an output terminal (2a) through a series connection of resistor (R1), input and output leads of an amplifier (12), and a sense circuit (22). The sense circuit controls two current sources (14),(16) in response to the shunt voltage and series current available from the telephone base. Current source (14) connects the amplifier output to an input terminal (1a) and acts either as a bias current source, or as an electronic switch that provides a short circuit from the microphone to the the amplifier output. Current source (16) connects in series between the amplifier ground lead and a common terminal (2b) and acts either as a bias current source, or as an electronic switch to enable or disable the amplifier. The sense circuit has negligible series or shunt effect on voice signals except when a carbon microphone is being emulated, at which time it provides additional amplification to the voice signals at the amplifier output. Overall amplification is controlled by a negative feedback loop (20) which connects from terminal (2b) to the the amplifier input.

Precision transconductance amplifier

Abstract: A transconductance amplifier intended for high frequency, precision amplification. The amplifier has a unique architecture that sets gain by the ratio of two impedances. Unlike conventional amplifiers, the amplifier does not use external feedback. This makes the amplifier unusually stable since one needn't worry about phase shift due either to the amplifier or a feedback network. Consequently, the amplifier can be used in some rather unusual circuit applications, some of which would be impossible with conventional (feedback) amplifiers. Various embodiments are disclosed.

Class D MOSFET amplifier and voltage supply balance circuit therefor

Abstract: The invention is directed to an improved electronic circuit using MOSFET (FET) devices for use in a first embodiment as a class D amplifier and in a second embodiment as a voltage balance circuit for a class D amplifier. In the first embodiment the operating functions of a conventional class D MOSFET amplifier is improved by the addition of a pair of Schottky diodes one of which is connected between the source terminals of the FETs and another connected between the drain terminals of the FETs and the addition of a pair of inductors one connected between the source of one FET and a third inductor and the other connected from the drain of the other FET to the third inductor. The other side of the third inductor provides the output of the class D amplifier. In the second embodiment, the circuit of the first embodiment is converted to a voltage balance circuit by grounding the output end of the first two inductors.