Showing papers on "FET amplifier published in 1993"

High-Power GaAs FET Amplifiers

Abstract: Introduction and basic theory high-power GaAs FETs computer-aided design of GaAs FET power amplifiers high-power GaAs FET amplifier design thermal effects and reliability combining techniques systems applications of GaAs FET power amplifiers.

Radio frequency power amplifier having variable output power

Abstract: A radio-frequency amplifier (50) has an impedance transformation network (66) with a control input (70) for controlling the transformation characteristic of the transformation network (66). The radio-frequency amplifier (50) amplifies an input signal to produce an amplified radio-frequency output signal to a load (68). The control circuit selects a power level for the output signal, in response to a control signal, by transforming the impedance of the load to a transformed impedance at the output of the radio-frequency amplifier, so that the efficiency of the radio-frequency amplifier is not substantially degraded as the power level for the output signal is changed.

Erbium-doped fibre amplifier with shaped spectral gain

Abstract: The spectral-gain characteristics of an erbium-doped fibre amplifier have been tailored by incorporating a gain-shaping-filter within the amplifier. The filter is chosen to modify the natural gain spectrum of the amplifier so as to suppress the gain peak and thus flatten the overall spectral-gain profile. Because the amplifier is distributed, it is possible to insert one or more filters along the length of the fibre. It is shown that there are considerable advantages to locating the filter within the length of the amplifier, rather than at the end, which is the more obvious choice. Advantages are that the amplifier pump efficiency is almost unaffected and the output saturation power is similar to that of the unshaped amplifier. In addition, the flat spectral gain provides an amplifier ideally-suited for use at a number of signal wavelengths, as required for wavelength-division multiplexing (WDM). The invention therefore comprises both the concept of filtering to shape the gain response of the amplifier and the recognition that this can be achieved without penalty by careful location of one or more filters along the length of the amplifier.

Pin driver amplifier

Abstract: A pin driver amplifier having a complementary pair of transistors with a pair of resistors coupled between the respective emitters. A node between the resistors is coupled through an output series resistor to an output terminal adapted for connection of a transmission line that conducts driver pulses of predetermined voltage levels and timing to a device under test. A capacitor is tied between the emitters to provide a substantially constant reverse termination impedance for the transmission line thereby reducing reflections. Also, an RC network is coupled between the output terminal and ground to further reduce reflections. The amplifier transistors are driven by respective buffer transistor emitters that are tied together by a capacitor to make the positive and negative going drive capabilities for the amplifier transistors more equal. Further, capacitors are coupled between the amplifier collectors and ground to provide a bypass for parasitic inductance in the supply voltage wires.

Operational amplifier using bipolar junction transistors in silicon-on-sapphire

Abstract: A method for fabricating low leakage current bipolar junction transistors of silicon-on-sapphire for efficient use in operational amplifiers utilizes all implant technology, improved silicon conditioning processing, and low temperature annealing.

Inverting output driver circuit for reducing electron injection into the substrate

Abstract: A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to VCC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to VCC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to VCC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.

Integration circuit including a differential amplifier having a variable transconductance

Abstract: An integration circuit includes a differential amplifier constituted by at least two bipolar transistors serving as amplifying elements, a capacitor connected, as a load, across the collection electrodes of the differential amplifier, and a field-effect transistor having source and drain electrodes connected between the emitter electrodes of the two bipolar transistors. A control voltage is applied to the gate electrode of the field-effect transistor. By changing the resistance value between the source and drain electrodes of the field-effect transistor using a gate voltage, the transconductance of the differential amplifier is changed over a wide range. As a result, the time constant of the integration circuit is changed, such that if the integration circuit is used for an active filter, for example, the cut-off frequency can be changed by changing the time constant of the integration circuit.

A quasi-optical amplifier

Abstract: A quasi-optical amplifier suitable for Gaussian-beam applications is presented. The amplifier is based on the integrated horn antenna and uses polarization duplexing to isolate the output beam from the input beam. A prototype hybrid amplifier is reported with a measured gain of 10.5 dB at 5.92 GHz. The amplifier design is uniplanar, is compact, and is compatible with the fabrication process of high-electron-mobility transistors (HEMTs) at millimeter-wave frequencies. >

High frequency power amplifier

Abstract: PURPOSE: To reduce current consumption of the high frequency power amplifier at the time of power reduction and to improve a linear modulation wave in distortion at the time of a maximum output, simultaneously and automatically. CONSTITUTION: A directional coupler 19 inserted to an input section of a post- stage amplifier 18 extracts part of input high frequency power of a pre-stage amplifier 17. The extracted power is superimposed onto a signal at a gate terminal of a post-stage FET 12 via a DC voltage generating circuit 28. Then a bias of the FET 12 is automatically controlled to an optimum value in response to an output level required for the power amplifier. COPYRIGHT: (C)1995,JPO

Differential amplifier having rail-to-rail input capability and square-root current control

Abstract: A differential amplifier contains a pair of differential portions (10 and 12) that together provide representative signal amplification across the full amplifier power-supply voltage range. Each differential portion normally contains a pair of like-polarity differentially coupled FETs (Q1 and Q2, Q3 and Q4) that divide a tail current (IN, Ip) into a pair of main currents (I1 and 12, 13 and 14). The two FET pairs are complementary. A square-root circuit (24) controls the tail currents in such a way that the sum of their square roots is largely constant. Consequently, the amplifier transconductance is largely constant.

Planar MESFET transmission wave amplifier

Abstract: The authors present a quasioptical power combining transmission amplifier for increasing the power level available from solid-state circuits. Receiving and transmitting arrays of patch antennas, input/output isolation, MESFETs, bias and matching circuitry are contained on a single substrate, making monolithic millimetre-wave integration possible. The flexibility of selecting input polarisation with respect to the output while maintaining amplifier stability is demonstrated. A 24-MESFET patch antenna amplifier array is presented.

Rectifier for DC/DC converter

Abstract: A rectifier for a DC/DC converter includes first and second FETs, first and second capacitors, and first and second resistors. The first FET is connected in series with the secondary winding of a main transformer of the DC/DC converter. The second FET is connected in parallel with the series circuit constituted by the secondary winding of the main transformer and the first FET. The first and second capacitors are respectively connected between the gate of the first FET and the drain of the second FET and between the gate of the second FET and the drain of the first FET. The first and second resistors are respectively connected between the gate and source of the first FET and between the gate and source of the second FET.

Class-AB large-swing CMOS buffer amplifier with controlled bias current

Abstract: A class-AB large swing CMOS buffer amplifier with new error amplifier circuits is presented. The error amplifier accurately controls the quiescent current through the output transistors, thereby reducing the variation of the quiescent power dissipation due to process and temperature variations. The buffer amplifier fabricated using 1.2- mu m CMOS technology occupies an area of 103 mil/sup 2/ and dissipates an average of 4.7 mW under the quiescent condition with the standard deviation of only 3.2% of the average value. It has -63.6 dB THD with 3.5 V/sub pp/ output swing into a 300 Omega /150 pF load at 5 kHz. >

Wide dynamic range optical receivers

Abstract: A wide-dynamic range optical receiver amplifier is provided by using two separate amplifiers. The first amplifier is a low-impedance input, low-noise, high-gain amplifier, preferably a transresistance amplifier. An input resistor is chosen for the amplifier such that its resistance value is much greater than the input impedance of the first amplifier, resulting in insignificant change in input impedance when the first amplifier's output becomes saturated. A light-induced signal source is connected to the input resistor such that signal current from the light-induced signal source flows through the input resistor into the first amplifier input. A second high-input-impedance amplifier (preferably an FET-input buffer amp) is connected to receive the light induced signal source, either directly or through a resistive divider network. The difference in gain between the two amplifiers serves to extend the dynamic range of the optical receiver amplifier without switching input or feedback components, and without discontinuous response as the first amplifier becomes saturated. Other embodiments are directed to a further diode induced breakpoint, and to a front-end for a spot tracking system.

High frequency plasma power source and impedance matching device for supplying power to a semiconductor processing apparatus

Abstract: In a high frequency plasma power supply comprising a final stage push-pull amplifier 2 with each phase having a parallel combination of at least two FETs, an output transformer 5 having the connection of the phase outputs of the push-pull amplifier 2 to the opposite terminals of a primary winding with a neutral tap, and a low pass filler 6 allowing passage of substantially the fundamental frequency component from the secondary winding output of the output transformer 5, the high frequency power passing through the low pass filter being supplied between the electrodes of a plasma chamber 10 through an impedance matching circuit 9 having an impedance adjusting mechanism, the dc voltage Vds to be applied between the drain and source of each FET of each phase of the push-pull amplifier is adjusted to not more than about 30% of the dc absolute rated value and the turn ratio of the output transformer is 1:4, thereby supplying the power having the level necessary for plasma reaction.

A Ka-band HEMT MMIC 1 watt power amplifier

Abstract: A 34-36-GHz, 1-W, 9-dB-gain monolithic microwave integrated circuit (MMIC) power amplifier which utilizes 0.15- mu m pseudomorphic InGaAs-GaAs high-electron-mobility transistor (HEMT) process technology is discussed. Power amplifier sites across the wafer were fully characterized with an on-wafer pulsed large-signal S-parameter test set. Test results from these amplifier chips showed output powers >30 dBm, with >9-dB gain, and power-added efficiencies >20%. Overall chip size is 4.8 mm*2.3 mm. A two-stage power amplifier module using one chip to drive three chips has been developed. The resulting amplifier module has achieved 3-W output power and 17-dB gain from 34-36 GHz. >

Low power consumption process-insensitive feedback amplifier

Abstract: A low power consumption amplifier that is essentially insensitive to the process used to fabricate the active devices of the amplifier employs feedback to minimize variations in electrical characteristics of the devices. For weight-sensitive microwave applications, a high electron mobility transistor (HEMT) or a pseudomorphic high electron mobility transistor (PHEMT) may be selected as an active device for each stage of the amplifier. HEMTs and PHEMTs typically exhibit greater device gain than do MESFETs, especially at the upper portion of X-band and above, so that a HEMT- or PHEMT-based stage of an amplifier where additional overall gain is required, can be achieved without significantly adversely affecting power consumption demands, and attendant electrical energy storage/generation requirements while achieving and/or maintaining an overall flat gain characteristic of the amplifier.

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays

Abstract: A high-speed small-area DRAM sense amplifier with a threshold-voltage (V/sub T/) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V/sub T/ mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V/sub T/ mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays. >

A high-performance monolithic Q-band InP-based HEMT low-noise amplifier

Abstract: The authors report a Q-band two-stage MMIC low-noise amplifier based on 0.1- mu m pseudomorphic InAlAs-InGaAs-InP HEMT technology. The amplifier has achieved an average noise figure of 2.3 dB with associated gain of 25 dB over the band from 43 to 46 GHz. This noise figure is the best result ever reported for a monolithic amplifier at this frequency range. In addition, this InP-based amplifier consumes only 12 mW, which is at least three times lower than a GaAs-based counterpart, indicating that InP-based pseudomorphic HEMTs are well suited for very high density monolithic integration or an application where ultra-low-power consumption is required. >

Preamplifier for optical communication having a gain control circuit

Abstract: A phase-inverting amplifier includes an input-stage FET, a load thereof and a gain control circuit. The gain control circuit is provided in parallel with the load, and reduces an effective load resistance to lower an open-loop gain of the phase-inverting amplifier when a current flowing through the load exceeds a predetermined value. The gain control circuit is typically a FET whose gate is biased at a constant voltage. A feedback resistor is provided in a negative feedback path of the phase-inverting amplifier. A bypass circuit is provided in parallel with the feedback resistor, and reduces an effective feedback resistance when a feedback quantity exceeds a predetermined value.

Zero-voltage complementary switching high efficiency class D amplifier

Abstract: A high-efficiency Class D amplifier is described. In one embodiment, the amplifier contains two transistors which are turned on and off in sequence, the output being taken from the common node between the transistors. The efficiency of the amplifier is substantially increased by insuring that voltage across each of the transistors is substantially zero when it turns on. This advantage is achieved by connecting an inductance to the common node, so that the electrical energy stored in any stray capacitance is transferred to the inductance before any transistor is turned on.

Temperature-compensated gain-controlled amplifier having a wide linear dynamic range

Abstract: A high dynamic range linear automatic gain control (AGC) circuit that has independent means for temperature compensation. The temperature compensation circuit of this invention can be used in a closed-loop AGC circuit such as is required in a transceiver for compensating the gains of receiver and transmitter amplifiers (16, 18) to ensure that both track closely over ranges of temperature, frequency and load impedance. The temperature compensation signal is coupled to one of the two gates in a field effect transistor (FET) amplifier to maintain a constant gain function over ranges of temperature, frequency and load impedance. Thermal compensation for the transmitter amplifier (18) is derived from the thermal compensation signal (28) for the receiver amplifier (16).

RF variable gain tuned output amplifier which maintains high Q in saturation

Abstract: An amplifier with variable gain which maintains high Q when saturated. A resonant circuit is connected between collector outputs of a differential pair of transistors and RF chokes couple DC supply current to the transistors. The chokes have a high impedance at the desired frequency. The emitters of the differential pair of transistors couple together to form a common output which is connected to a current source. The amount of current from the current source substantially controls the gain of the amplifier. Because the resonant circuit is not shunted with a low impedance even when one of the transistors saturates, the Q of the resonant circuit is maintained.

Superconducting resonator and a cryogenic GaAs field‐effect transistor amplifier as a single‐ion detection system

Abstract: A current measuring system capable of detecting single ions is described The detector operates at a frequency of nominally 900 kHz and utilizes a superconducting inductor with high Q(Q≊8500) and a cryogenic GaAs field‐effect transistor (FET) amplifier with noise temperature less than 03 K Noise measurements of the FET are presented along with details of the construction of the superconducting inductor

Differential amplifier with mismatch correction using floating gates

Abstract: Differential amplifier (10) incorporates five metal oxide field effect transistors (MOSFETs) (M1 to M5). The transistors (M1 to M5) are a source-coupled pair of input transistors (M1, M2) with sources connected to a current control transistor (M5) and having respective drain load transistors (M3, M4). The transistors (M1 to M5) have floating gates (F1 to F5) and input gates (G1 to G5). The amplifier (10) is adjusted to counteract differing input transistor threshold voltage by charging one of the input transistor floating gates (G1 , G2) to reduce amplifier offset voltage extrapolated to zero input transistor drain current. It is then adjusted to reduce discrepancies between actual and design values of input transistor drain voltage by charging one or both of the drain load transistor floating gates (F3, F4). The amplifier may be arranged as an operational amplifier (20) with a second state (16) connected to an input transistor drain. The operational amplifier input offset voltage is determined by comparing the second stage output with a reference and feeding a resulting differences signal to the amplifier input. The input offset voltage is then counteracted by charging an input transistor floating gate (F1 or F2) to reduce the difference signal.

Stable, narrow bandwidth, high frequency amplifier with low power consumption

Abstract: A low noise narrow band amplifier with low power consumption for amplifying radio frequency and microwave signals. The amplifier includes a high frequency transistor that has a cut-off frequency greater than the center frequency of the input signal. The amplifier includes an emitter inductor for low noise and better input match. The amplifier is stabilized for out-of-band high frequency oscillations by a collector inductor and a base inductor. The amplifier is further stabilized unconditionally for out-of-band high frequency oscillations by a stabilizing circuit coupled between the output and ground, including a stabilizing capacitor in series with a stabilizing resistor.

High efficiency RF power amplifier

Abstract: A control network operates a GaAs FET with a quiescent current closer to the maximum output current, Imax, than to zero current. An output network couples the FET to the load and is characterized as having a low impedance at a fundamental frequency and a high impedance lower than an open circuit impedance at at least the second harmonic frequency. As a result, the peak voltage on the output terminal is greater than two times the supply voltage. A preamplifier raises the level of the input signal so that it has a positive voltage peak when biased by the control network and applied to the input terminal. This overdrives the FET and produces an output current that is at the maximum output current level for a longer time during each cycle than the output current is at a minimum level. This enhances the effect of the output network to produce an output voltage spike on the FET that is several times the DC voltage. The amplifier is part of an amplifier system that also includes a switch coupled between the DC supply and the FET that is responsive to a control signal. A circuit is responsive to the input signal for generating the control signal appropriate for disconnecting the DC voltage supply from the FET when there is no input signal.

High-frequency power amplifier device with drain-control linearizer circuitry

Abstract: A two-stage power amplifier device for use in a digital hand-held radiophone includes a first and a second amplifier circuit. The first amplifier is an exciter-stage amplifier for receiving a high-frequency input signal corresponding to a modulation signal to generate an amplified signal at its output. The second amplifier is a final-stage amplifier connected to either the input signal or the output of the exciter amplifier. A detector circuit is connected to the exciter amplifier, for monitoring variations in a bias current to be fed to the exciter amplifier, and for generating a detection signal indicative of the current variation thus detected. A linearizer circuit is connected to the detector and the final-stage amplifier. The linearizer is responsive to the detection signal, for forcing a bias voltage given to the final-stage amplifier to vary in potential while causing the bias voltage to remain in a univocally determinable relationship with a waveform of said input signal, to thereby increase the linearity of the final-stage amplifier.

Self biased power amplifier employing FETs

Abstract: A power amplifier for microwave frequencies utilizes a FET device operating from a common voltage source. The voltage source has the positive terminal coupled to the drain electrode of the FET. The gate electrode of the FET is adapted to receive a RF signal while the source electrode of the FET includes a voltage limiting diode that is in parallel across the source impedance. In operation the extra current required from the voltage source during power amplification is passed through the diode and the FET source bypass capacitor. This results in the FET source voltage remaining relatively constant to enable improved power and gain operation.

Trigger circuit for a power FET with a load on the source side

Abstract: A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between the first input terminal and the gate terminal of the first power FET. A second FET of the opposite channel type from that of the first power FET has a gate terminal and has drain and source terminals defining a drain-to-source path. A second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of the second FET to the drain terminal of the power FET. A resistor is connected between the gate and source terminals of the second FET. A controllable switch is connected to the gate terminal of the second FET. A second input terminal is connected to the controllable switch for receiving a voltage being lower than a supply voltage. A third depletion FET has a gate terminal connected to the controllable switch and has drain and source terminals defining a drain-to-source path connected between the gate terminal and the source terminal of the first power FET for discharging a gate-to-source capacitance of the first power FET.