Showing papers on "FET amplifier published in 1998"

Dual-band, dual-mode power amplifier

Abstract: A power amplifier circuit for a radio transceiver has a linear mode amplifier and a saturated (nonlinear) mode amplifier, a diplex matching circuit coupled to the linear mode amplifier for impedance matching and for separating transmitted signals in a plurality of frequency bands, a low pass matching circuit coupled to the output of the saturated mode amplifier and means for selectably placing the power amplifier circuit in a linear mode for or a saturated mode, corresponding to digital and analog modes of operation of the cellular telephone, respectively in linear or digital mode, the linear amplifier is biased in the on state and the saturated mode amplifier may be biased in the off state. Similarly, in the saturated or analog mode of operation, the saturated mode amplifier is biased in the on state and the linear amplifier may be biased in the off state. The amplifier circuit may include a switch or circuit, coupled to an output of the diplex matching circuit and the output of the low pass matching circuit, for selectably coupling the first diplex matching circuit output or the low pass matching circuit output to an output line when the amplifier circuit is selectably placed in linear mode or saturated mode, respectively.

Sense amplifier circuit

Abstract: This invention provides a sense amplifier circuit capable of determining an output with small power consumption at high speeds and simplifying a control signal. The sources of a pair of driver nMOS transistors in a first amplifier are connected to VSS via an activation nMOS transistor. An output from the first amplifier is directly input to input/output nodes of a second, latch amplifier. The sources of a pair of nMOS transistors in the second amplifier are connected to VSS via an activation nMOS transistor. The input/output nodes are precharged to VCC by a precharge circuit in a standby state. The activation nMOS transistors are simultaneously controlled by a clock signal, and the first and second amplifiers are simultaneously activated to sense, amplify, and latch the potential difference between input/output nodes.

Power amplifier output module for dual-mode digital systems

Abstract: A power amplifier output module 200 having low insertion loss and self-shielding properties for dual-mode digital systems is provided. Module 200 has a first power amplifier drive circuit comprising a first power amplifier 220 and a first output impedance matching network having integrated suppression of higher order harmonics 222. A second power amplifier drive circuit comprising a second power amplifier 224 and a second output impedance matching network having integrated suppression of higher order harmonics 226 is also provided. Module 200 also comprises a single diplexer 228 coupled to the first impedance matching network and the second impedance matching network. Module 200 also comprises a single broadband directional coupler 230, coupled to the diplexer 228, for coupling both the first power amplifier drive circuit and the second power amplifier drive circuit. Module 200 provides an integrated solution involving greater performance in a smaller package.

Impedance matching circuit for power amplifier

Abstract: An impedance matching circuit for a multi-band power amplifier has an input port for receiving RF signals from an amplifier, a first path for communicating RF signals in a first frequency band to a first output port, and at least one second path for communicating RF signals in a second frequency band to a second output port. The first path includes impedance matching circuitry for matching the impedance of the first output port and the input port in the first frequency band, and the second path includes impedance matching circuitry for matching the impedance of the second output port and the input port in the second frequency band. The first path contains circuitry which blocks RF signals in the second frequency band; and the second path contains circuitry which blocks RF signals in the first frequency band. A multiband power amplifier includes a multi-band amplifier coupled with an impedance matching circuit for a multiband power amplifier.

A low-voltage low-power wide-range CMOS variable gain amplifier

Abstract: In this paper, a compact low-power (LP) low-voltage (LV) metal-oxide-semiconductor-only (MOS-only) variable gain amplifier (VCA) is introduced. This amplifier based on complementary MOS (CMOS) transistors operating in strong inversion is composed of a pseudo-exponential current-to-voltage converter, analog multiplier, and output stage. The gain of the amplifier is controlled exponentially by a novel wide-range pseudo-exponential current-to-voltage converter implemented with two back-to-back connected current mirrors exhibiting superb exponential characteristic. Also, a new LV/LP composite transistor is introduced to increase the input dynamic range of the multiplier. The amplifier is fabricated using a 2-/spl mu/m MOSIS n-well process, and its simulation and measurement results are shown in detail.

Dual-band, dual-mode power amplifier with reduced power loss

Abstract: A power amplifier circuit has a driver amplifier stage including a low band driver amplifier and a high band driver amplifier. A final amplifier stage includes a linear mode amplifier for amplifying digitally modulated signals and a saturated (nonlinear) mode amplifier for amplifying frequency modulated (analog) signals. A switching network interconnects the driver amplifier stage and the final amplifier stage. Depending on the desired mode of operation, an appropriate driver amplifier can be coupled to an appropriate final amplifier to most effectively and efficiently amplify analog or digital RF signals in either of a plurality of frequency bands. A matching circuit is coupled to the linear mode final amplifier for impedance matching and for separating D-AMPS (800 MHz band) and PCS (1900 MHz band) digital signals. A power impedance matching circuit is coupled to the output of the saturated mode final amplifier. In one embodiment, an isolator is coupled to the output of one or more of the low band or high band outputs of the duplex matching circuit. In the low band analog path, a duplexer is provided ahead of the coupling means for reducing the RF power requirements on the coupling means. The switching network and input filter stage may precede a driver amplifier stage.

Wide band optical amplifier

Abstract: A wide band optical amplifier employing a split-band architecture in which an optical signal is split into several independent sub-bands which then pass in parallel through separate branches of the optical amplifier. Each branch may be optimized for the sub-band that traverses it. The independent sub-bands are combined before output, resulting in a broad band, high efficiency amplifier. Alternative, hybrid split-band amplifiers are described. As a result of their desirable characteristics, these wide band optical amplifiers may be used in dense WDM communications systems.

Differential sense amplifier circuit

Abstract: A sense amplifier having four NMOS transistors and two resistors is operable at voltage supplies less than 2.5 volts and has a fast response time. The drain terminals of two of the NMOS transistors, each receiving an input voltage signal at its gate terminal, provide a differential output voltage signal across the two resistors. The source terminals of these two NMOS transistors are coupled to the drain and gate terminals of a cross-coupled second pair of NMOS transistors. The amplifier exhibits negative input capacitance at each of its input terminals. The amplifier has a common mode input voltage that is substantially equal to the common mode output voltage, facilitating the cascading of many stages of the amplifier. Each stage of a multi-stage cascade of the amplifiers has a greater than unity voltage gain if driving a low capacitance line or a smaller than unity gain if driving a high capacitance line.

High-efficiency harmonic-control amplifier

Abstract: A half-sinusoidally driven class-A harmonic-control amplifier (hHCA) combines the advantage of high gain of class A with the advantage of high drain efficiency of class F. Consequently, power-added efficiency is increased as compared with state-of-the-art high-efficiency amplification techniques. As this innovative amplifier concept consists of a pulse-forming class-B amplifier stage followed by a class-A power-amplifier stage, intermodulation distortion is low even in saturation. The realization of such a two-stage hHCA offers 71% overall efficiency, 27.9 dBm output power, and 22.4 dB gain at 1.62 GHz. Two-tone measurements at 1 dB gain compression, where the amplifier's single-carrier (SC) overall efficiency is still 64%, has demonstrated thirdand fifth-order intermodulation distortion of -29 and -21 dBc, respectively.

Power amplifier incorporating heterojunction and silicon bipolar transistors

Abstract: A power amplifier including an amplifier stage including a heterojunction bipolar transistor for signal amplification having a base electrode connected to an RF signal input terminal, and a grounded emitter electrode; and a bias circuit including a silicon bipolar transistor having a base electrode connected to a power supply terminal, and a terminal from which a current amplified in response to a base current is output, which terminal is connected to the base electrode of the heterojunction bipolar transistor stage. In this power amplifier, since the voltage required for operating the bias circuit is reduced, a power amplifier capable of operating at a low voltage is realized.

Partial or complete amplifier bypass

Abstract: A power amplifier circuit arrangement particularly useful for portable phones used in wireless systems. A power amplifier stage can be partially or completely bypassed so that multi-stage amplifiers can be built that allow wide dynamic range of power amplification to be obtained efficiently. A switch at the input of an amplifier stage couples an input signal either to an amplifier or to a bypass path. The output of the amplifier is coupled to a first impedance-transforming network. The bypass path includes a second impedance-transforming network. A third impedance transforming network couples the outputs of the first and second impedance transforming networks. The impedance transforming networks are constructed and arranged so that input and output signals see the correct load regardless of whether the amplifier is used or bypassed. Using the principles of this invention, multi-stage amplifiers can be constructed including input and bypass attenuators to achieve a wide range of gain levels.

Complimentary metal oxide semiconductor imaging device

Abstract: A CMOS imager includes a photosensitive device such as a photosensitive device such as a photodiode or photogate having a sense node coupled to an FET located adjacent to the photosensitive region. Another FET, forming a differential input pair of an operational amplifier is located outside of the array of pixels. The operational amplifier is configured for unity gain and a row or column of input FETs is connected in parallel. A correlated double sampler is connected to the output of the operational amplifier for providing a fixed pattern noise free signal.

Amplifier with active bias compensation and method for adjusting quiescent current

Abstract: An active bias compensation circuit (110) senses a quiescent current flowing in an amplifier (130) and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier (130) over a wide range of factors, e.g., temperature variation, process variation, history of the amplifier (130), etc. The compensation circuit (110) includes two transistors (101, 102) forming a difference amplifier. A sensing voltage proportional to the quiescent current and a reference voltage are applied to the base electrodes of the two transistors (101, 102), which generates a bias signal in response to a difference between the sensing voltage and the reference voltage. The bias signal adjusts the quiescent current in the amplifier (130).

A new high-efficiency and super-fidelity analog audio amplifier with the aid of digital switching amplifier: class K amplifier

Abstract: This paper presents an audio amplifier that simultaneously has the advantages of digital and analog amplifier. The high efficiency is achieved by the digital amplifier, which is playing a role of dependent current source. The high fidelity is guaranteed by the analog amplifier playing a role of independent voltage source. Experimental results show that the proposed amplifier has 0.005% total harmonic distortion (THD) and around 90% power efficiency at 50 W output.

Short-circuit protection and over-current modulation to maximize audio amplifier output power

Abstract: A Class D amplifier includes a tracking circuit and a regulation circuit to provide efficient, accurate protection against excessive current flow in the power FET's of the amplifier output stage. The FET currents flowing in the output stage are mirrored across tracking resistors by the tracking circuit. The resultant voltage drops are compared to reference voltages to detect over-current situations. By mirroring scaled-down versions of the output currents, power consumption in the tracking circuit is minimized. When an over-current situation is detected, the regulation circuit modulates the duty cycle of the signal input to the output stage until the FET currents fall to acceptable levels. If two over-current indications occur during a single clocking cycle of the pulse-width modulator of the amplifier, the regulation circuit shuts off the amplifier to protect against short-circuit damage.

Dittributed feed back distributed amplifier

Abstract: A distributed amplifier topology with distributed feedback includes a plurality of amplifier stages, each of which includes a FET, MESFET or HEMT. A negative feedback network is provided with each amplifier stage which enables the gain of the distributed amplifier to be reduced by varying the negative feedback. An important aspect of the invention relates to the fact that the gain can be varied with virtually no affect on the bandwidth performance of the product and without significantly affecting the return loss, IP3 and noise figure performance of the device.

Impedance matched CMOS transimpedance amplifier for high-speed fiber optic communications

Abstract: A transimpedance amplifier according to the present invention is designed for high-speed fiber optic communications. The transimpedance amplifier preferably includes an input stage, a second stage and a bias generator. The input stage is operably coupled to the second stage and has an input impedance. The second stage has an output impedance. The bias generator is operably coupled to the input stage and the second stage, and operates to bias the input stage and second stage such that the input impedance substantially matches the output impedance. In this manner, the input and output impedances of a transimpedance amplifier of a fiber optics communication receiver are controllable to a desired impedance for interfacing with a transmission line.

A low-cost class-E power amplifier with sine-wave drive

Abstract: We present a 400 W class-E amplifier for industrial applications. The transistor is the International Rectifier IRFP450LC power MOSFET. The amplifier operates at 13.56 MHz and uses a drive level of 12 W to attain a drain efficiency of 86% and an overall efficiency of 84%. All harmonics are more than 40 dB below the carrier.

Multi-stage high-performance amplifier

Abstract: A two-stage switched-capacitor CMOS Miller-compensated amplifier uses only n-channel transistors in its signal path to reduce the deleterious effects of parasitic capacitances in the signal path while still obtaining a high transconductance in both stages. A transistor inserted in series with the Miller capacitor between the output and input of the second stage of the amplifier introduces a feedforward zero in the left half of the S-plane of the circuit. By appropriately sizing the aspect ratio and properly biasing this transistor, the second pole of the amplifier is canceled with the introduced zero. Dummy transistors having their sources and drains connected (to serve as capacitors) are cross-connected between opposite polarity inputs and outputs of a differential pair of input transistors in the first stage to effectively cancel the gate-to-drain Miller-multiplied capacitance of the input transistors. A common-mode control current is generated based upon a voltage at a common-source node of a differential pair of input transistors in the second stage. This current is fed back to the first stage to control the common-mode of the first stage.

High speed, fine-resolution gain programmable amplifier

Abstract: An integrated circuit differential amplifier with a digitally controllable gain. In a preferred embodiment, the differential amplifier employs first and second transconductance (gm) amplifiers and a digital to analog converter (DAC). The first gm amplifier converts a differential input voltage into a differential output current and the second gm amplifier converts the differential output current into a differential output voltage. A digital input code is applied to the DAC to generate an analog output voltage that is applied to one of the gm amplifiers to control its transconductance to thereby control the gain of the differential amplifier. The second gm amplifier employs a pair of low impedance feedback paths between input/output terminals of opposite polarity. The gain of the differential amplifier is thus a function of the ratio of the transconductance of the first gm amplifier to that of the second gm amplifier. Preferably, the same circuit topology is employed for both gm amplifiers, leading to a process- and operating temperature-insensitive differential amplifier gain. Additional gm amplifiers may be connected in parallel with the first gm amplifier to enhance gain. The load resistance presented by the second gm amplifier is preferably kept low to afford high speed operation.

Cascaded error correction in a feed forward amplifier

Abstract: A feedforward amplifier system including a main amplifier and first and second error amplifiers, and wherein the first error amplifier is itself a feedforward amplifier whose operation is corrected by the second error amplifier. With appropriate selection of circuit components the operating power required by the amplifier system, and hence the size of the package in which it is contained, may be reduced up to one-third.

A 1.9 GHz single-chip RF front-end GaAs MMIC with low-distortion cascode FET mixer for personal handy-phone system terminals

Abstract: This paper describes new single-chip RF front-end GaAs MMIC for 1.9 GHz Japanese PHS handheld terminals. The IC consists of a high power amplifier, a T/R switch, a low noise amplifier, a newly developed low distortion cascode FET mixer and a negative voltage generator for FET gate bias voltage. The IC has high performance as an RF front-end for PHS terminals.

Device design for enhanced avalanche SOI CMOS

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

High-fidelity and high-efficiency analog amplifier combined with digital amplifier

Abstract: This invention provides an analog audio amplifier having both excellent linearity and high efficiency, which is combined with digital amplifier. The analog-digital combined amplifier comprises a class A, class B or class AB type analog amplifier serving as an independent voltage source; and a class D type digital amplifier serving as a dependent current source thereof, wherein the analog amplifier and the digital amplifier are connected to each other.

On the noise properties of balanced amplifiers

Abstract: The balanced amplifier is used in applications requiring a better input match than is possible with a single-ended amplifier. While the impedance matching property of the balanced amplifier is well known, its noise behavior appears not to be widely understood. It is shown that the outgoing noise waves at the input and output of a balanced amplifier are uncorrelated even though they originate in the same components. Hence, a sliding short-circuit at the input produces no variation in the output noise of the amplifier. The properties of a balanced amplifier are similar to those of an amplifier preceded by an isolator, although the noise wave emerging from inputs of the two circuits originates in different elements. The noise theory of the balanced amplifier applies also to balanced mixers based on quadrature hybrids.

Semiconductor nonvolatile memory device in which high capacitance bit lines are isolated from sense amplifier input/output nodes during amplifying operation of sense amplifier

Abstract: In the semiconductor memory device which has nonvolatile memory cells, the bit lines which are typified by high capacitances, are isolated from the input/output nodes of the corresponding sense amplifiers during the amplifying operation of the sense amplifier. A flip-flop circuit, such as a CMOS latch circuit, is used for each of the sense amplifiers and a switch circuit is connected between each input/output of each sense amplifier and the data (bit) line associated therewith and is turned OFF immediately before or after commencing of the amplifying operation of the sense amplifier. During the amplifying operation of the sense amplifier, the data (bit) line, having a large parasitic capacitance as a result of being typically connected to a large number of nonvolatile memory cell transistors, such as of the single transistor type having both a floating gate and control gate electrodes, is electrically disconnected (electrically isolated) from the sense amplifier.

CMOS differential amplifier having offset voltage cancellation and common-mode voltage control

Abstract: A differential amplifier for amplifying the difference between first and second input signals and producing therefrom a differential output signal. The differential amplifier includes first and second transistors connected to a common DC current source and receiving, at the transistor gate terminals, the respective first and second input signals. Each transistor has a common mode voltage associated therewith. A voltage control circuit generates control signals that are applied to the backgate terminals of the transistors to calibrate the differential output voltage and to adjust the common mode voltages of the transistors.

Transistor amplifier stage

Abstract: A transistor amplifier stage, in particular an RF amplifier stage with an npn amplifier transistor, which is coupled with its base to an alternating voltage input terminal, with its emitter to a fixed potential, and with its collector to an alternating voltage output terminal. An active operating point stabilization unit with a first and a second pnp transistor is provided between a direct voltage input terminal and the base of the npn amplifier transistor.

Active compensating capacitive multiplier

Abstract: A compensated amplifier, for amplifying an input signal applied to an input node to provide an output signal at an amplifier output node. The compensated amplifier includes a first amplifier stage having an internal node as an input thereto and having a first stage output node. Also included is a second amplifier stage coupled to the first amplifier stage, having the input node as an input thereto and providing the output signal at the amplifier output node. A capacitor is coupled between the output node and the internal node.

Apparatus and method for pre-distortion correction of a power amplifier stage

Abstract: In an amplifier circuit having an amplifier path, a new pre-distortion arrangement is provided. The amplifier circuit includes a signal source, an intermediate amplifier stage, and a power amplifier stage connected sequentially, in series along the amplifier path. The power amplifier stage includes one or more amplifiers operationally connected in parallel, and one or more pre-correction circuits. Each of the amplifiers subjecting an inputted signal to shifts away from their intended values. Each of the pre-correction circuits is associated with one of the amplifiers and connected between an output of the intermediate amplifier stage and the associated amplifier. Each of the pre-correction circuits pre-distorts the signal input to the associated amplifier to compensate for the distortion caused by the associated amplifier. Also, preferably, pre-correction circuits are associated with, and in series with, each of the amplifier stages for pre-distorting the signal input to the associated amplifier stage to compensate for the distortion shifts of the associated amplifier stage.