Showing papers on "FET amplifier published in 2003"

A microwave Doherty amplifier employing envelope tracking technique for high efficiency and linearity

Abstract: In this letter, we demonstrate a microwave Doherty amplifier employing an input signal envelope tracking technique. In the amplifier, the gate bias of the peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier is compared with that of a class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at -30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level.

Effect of baseband impedance on FET intermodulation

Abstract: The intermodulation performance of an FET in the common-source configuration is dependent on the impedance presented to its gate and drain terminals, not only at fundamental, but also at harmonic and baseband frequencies. At baseband frequencies, these terminating impedances are usually determined by the bias networks, which may have varying impedance over the frequencies involved. This can give rise to asymmetry in two-tone intermodulation levels, and changing intermodulation levels with tone spacing, as previous studies have shown. In this paper, an FET is analyzed to gain an understanding, useful to the circuit designer, of the contributing mechanisms, and to enable the prediction of bias points and the design of networks that can minimize or maximize these effects. Compact formulas are given to facilitate this. An amplifier was tested, showing good agreement between the theoretical and measured results.

High efficiency amplifier

Abstract: An amplifier includes a main amplifier circuit and at least one auxiliary amplifier circuit. Portions of an RF signal to be amplified are delivered to the main and auxiliary amplifiers. The auxiliary amplifier circuit is selectively operable to operate in combination with the main amplifier circuit, such as based on the level of the RF signal. At least one hybrid coupler circuit has input ports coupled with outputs of the main amplifier circuit and auxiliary amplifier circuit. The hybrid coupler circuit is operable to combine amplifier circuit output signals at a coupler first output port. A coupler second output port is terminated with one of an electrical short and an electrical open circuit.

Radio frequency power detecting circuit and method therefor

Abstract: A circuit for detecting the amount of radio frequency power provided by an amplifier. The circuit contains an array of coupled transistors in two power amplifiers, and a log-detector circuit, all resident on a single semiconductor die. The main power amplifier contains the larger array of transistors to amplify the radio frequency signal for feeding to an antenna, and a secondary power amplifier contains a smaller array of transistors to provide a scaled output that is proportional to the amplified radio frequency signal and is used to control the main power amplifier. The log-detector circuit converts the signal from the secondary power amplifier to a full-wave rectified log-linear DC signal that is logarithmically proportional to the controlling signal. The DC signal output from the log-detector circuit is fed to the main power amp to control it.

Integrated circuit radio front-end architecture and applications thereof

Abstract: An integrated RF front-end architecture is disclosed. Such an integrated RF front-end architecture includes a multi-tap balun, a low noise amplifier and a power amplifier core. The multi-tap balun includes a single-ended primary winding and a symmetrical multi-tap secondary winding, wherein the single-ended primary winding is operably coupled to an antenna. The low noise amplifier is coupled to a first set of taps of the symmetrical multi-tap secondary winding. The power amplifier core is coupled to a second set of taps of the symmetrical multi-tap secondary winding and can be a two stage amplifier having a driver stage and an output stage. The multi-tap balun, low noise amplifier and power amplifier core can be on-chip components or can be fabricated to be discrete components on a printed circuit board.

A fully-integrated bandpass amplifier for extracellular neural recording

Abstract: This paper describes a fully-integrated bandpass amplifier for neural recording applications. Diode-connected sub-threshold-biased NMOS transistors in the feedback loop of the amplifier realize the high on-chip impedance necessary to eliminate the dc baseline potential of the electrode while amplifying neural field and action potentials. The amplifier has an in-band gain of 38.2dB, a dc gain of 0, an upper cutoff frequency of 24kHz and a low frequency cutoff of 66mHz. It consumes 92/spl mu/W from /spl plusmn/1.5V supplies and has an input-referred noise of 16.6/spl mu/Vrms integrated from 100Hz-10kHz. The amplifier occupies 0.082mm/sup 2/ in 3/spl mu/m features and is being used on a 64-site neural recording probe.

High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM

Abstract: Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. This paper describes two sensing techniques to overcome this problem: a current sense amplifier (CSA) and a charge transfer sense amplifier (CTSA) and their implementation based on 90 nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier, for the same energy. The other is a charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. The CTSA shows an improvement of 18-22% for read delay for 128 memory cells and consumes 15-18% less energy than the voltage mode sense amplifier. The CTSA results in reduced bit-line swing, which in turn leads to 30% lower bit-line energy than the conventional voltage mode.

Low noise, low power consumption high electron mobility transistors amplifier, for temperatures below 1 K

Abstract: Low noise three-stage pseudomorphic high electron mobility field-effect transistors amplifier were designed for the temperature range below 1 K. A minimum noise temperature TN≈100 mK was measured at an ambient temperature of about 380 mK at frequencies between 1 and 4 MHz for a source resistance of 10 kΩ. The gain of the amplifier was 50 at a power consumption of about 200 μW. The noise parameters of the amplifier are stable to within 30%, for a power consumption in the range of 100–300 μW. Minimum voltage spectral noise density of the amplifier with respect to the input is about 200 pV/Hz1/2 and the corner frequency of the 1/f noise is close to 300 kHz.

Testing apparatus and method for thin film transistor display array

Abstract: A testing circuit and method for thin film transistor display array, for testing the yield of a thin film transistor array is provided. The testing circuit includes an array tester, a test panel (DUT) and a sense amplifier array. The sense amplifier is composed of a plurality of trans-impedance amplifier units and a plurality of parasitic capacitance discharge circuit units. Every sense amplifier includes a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance. The trans-impedance amplifier is used to form an integrated circuit and the output is transmitted to a sampling/hold circuit via a switch. Also included is a parasitic capacitance discharge circuit that is used to form a discharge route for the charge of the parasitic capacitance.

Coupled-inductance differential amplifier

Abstract: A differential amplifier that employs mutually coupled inductors to provide desired levels of inductance in a substantially smaller form factor in comparison to individual inductor components. Mutually coupled inductors according to the present teachings may also be used to increase common mode rejection in a differential amplifier.

Improved VCSEL analog optical link

Abstract: An improved analog VCSEL optical link includes the following elements listed in their downstream order from the input to the output: an RF preamplifier (A1) for receiving a bandpass RF signal; a first impedance matching network (LASINT) to match the input impedance of a downstream VCSEL laser to the output impedance of the RF preamplifier (A1); the VCSEL laser coupled to one end of a multimode optical fibre of given length for transducing optically the electrical bandpass RF signal; a PIN diode coupled to the other end of the multimode optical fibre for transducing into electrical the optical signal coming from the fibre; a second impedance matching network (C2, L2) to match the output impedance of the PIN diode to the input impedance of a downstream low-noise transimpedance amplifier (T1) and minimise the noise figure of said transimpedance amplifier (T1) in the meanwhile; the transimpedance amplifier (T1) including a low-noise FET in common source configuration; an RF power amplifier (A2); an RF signal envelope detector generating a control signal for a variable phase shifter placed downstream the RF power amplifier (A2) to compensate for the AM/PM distortion introduced by both the optical fibre and the power amplifier itself; and, if necessary, a gain linearisation network of the RF power amplifier (A2) and/or the RF preamplifier (A1). The analog VCSEL optical link is suitable for the following uses: connecting indoor apparatuses with tower antennas either static, i.e. point-to-point radio relay, or directive arrays, i.e. point-to-multipoint systems; building-up a fibre infrastructure for connecting centralised base stations with respective pool of remote antennas serving as many cells of a cellular telephone system such as: PCS, GSM, UMTS, and similar; intra-building connections for distributing, CATV services (fig.4).

EER modulator with power amplifier having feedback loop providing soft output impedance

Abstract: An EER amplifier for amplifying an RF signal includes: (II) a first RF amplifier for amplifying the phase portion of the signal; (III) an EER modulator for amplifying the envelope or baseband portion of the signal, including: A) a high frequency operational amplifier; B) a power amplifier; C) a feedback control loop including: (1) a current-to-voltage conversion amplifier having an input coupled to a current monitoring output of the power amplifier and an output, (2) an input buffer amplifier having an input coupled to receive the envelope signal and an output; (3) a summing amplifier having: (a) an input coupled to the outputs of: (a) the current­to-voltage conversion amplifier and (b) the input buffer amplifier, and (b) an output coupled to the current control input of the power amplifier.

Balanced radio frequency power amplifier with temperature compensation

Abstract: A radio frequency power amplifier has first and second amplifier transistors. The first and second amplifier transistors have a common element thereof electrically interconnected with a common bus. A forked conductor having two legs thereof electrically connected to the common bus, each leg having a distal end proximate one of the first and second amplifier transistors. The common bus and the forked conductor are generally symmetric about an axis about which the first and second amplifier transistors are symmetrically disposed.

Multi-mode/multi-band power amplifier

Abstract: The present invention provides a wideband power amplifier for a multi-mode or multi-band wireless communication device. The wideband power amplifier is configured to amplify signals in different frequency bands corresponding to different operating modes. In general, the wideband power amplifier includes multiple matching circuits that operate to combine the signals in the different frequency bands and provide a combined signal to each transistor in an output stage of the wideband power amplifier.

Highly efficient feed-forward amplifier using a Class-F Doherty amplifier

Abstract: A new feed-forward amplifier configuration is proposed that uses a Doherty amplifier with Class-F operation as the main amplifier. Due to the new configuration, the enhanced main amplifier operates well with less output back-off and achieves high efficiency under Class-F operation compared with Class-B amplifier (non Doherty amplifier). A 2-GHz band 1-W class feed-forward amplifier is investigated. A back-off improvement of 3 dB is experimentally achieved compared with a conventional feed-forward amplifier for the same intermodulation distortion level. The efficiency of the main amplifier is also improved from 33% to 52% when third-order intermodulation distortion of feed-forward amplifier is - 50 dB. The proposed technique can effectively reduce the power consumption of the power amplifiers for cellular base stations.

FET amplifier with temperature-compensating circuit

Abstract: A FET amplifier which minimizes the worsening of the distortion-susceptibility due to variations in the ambient temperature of operation is to be provided. An LDMOS FET 1 , whose source terminal is grounded and to which are applied a gate voltage Vgs from a gate bias terminal 3 via a temperature-compensating circuit 2 and a choke coil and a drain voltage Vds from a drain bias terminal 4 via a choke coil operates as a source-grounded type amplifier. In the temperature compensating circuit 2 , the resistances of fixed resistance elements 21 and 22 connected in parallel are set to be the same or have the same number of digits, and those of thermosensitive resistance elements (thermistors) 23 and 24 are set to be a combination of a value greater by one digit and a value smaller by one digit than that of the fixed resistance element 21 or the fixed resistance element 22 at the standard level (+25° C.) in the ambient temperature range of operation.

Multi-corner FET for better immunity from short channel effects

Abstract: A field effect transistor (FET) is described as having a channel in which there is at least one groove parallel to a length direction of the FET. A geometry of the groove is selected so as to increase short channel immunity of the FET.

Series/shunt switch and method of control

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Amplifier assembly with an adjustable performance

Abstract: An object of the present invention is to suggest an approach for providing an amplifier performance which is adjustable in particular with regard to a usable frequency range or frequency band of operation but also with regard to at least one further certain criterion, such as gain, bandwidth, efficiency, output power capability and linearity even when then amplifier is assembled. The invention proposes an amplifier assembly, in particular an RF-power amplifier assembly for use in mobile radio system, especially in an UMTS or GSM system, comprising at least one active amplifying device (1), with the input and/or with the output of said active amplifying device (1) being connected to at least one controllable reconfigurable circuit (2a,2b,2a',2b').

An 1 GHz class E LDMOS power amplifier

Abstract: A class E power amplifier working at 1 GHz and with an LDMOS transistor as switching element has been developed. The circuit is implemented with lumped and distributed elements. An output power of 6.2 W at 69 % drain efficiency with a gain of 11 dB was obtained at 1 GHz. Both simulations and measurements of the amplifier are presented within this paper. This is to our knowledge the highest efficiency and output power reported for a class E amplifier at 1 GHz.

Apparatus and method to provide power amplification

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to increase efficiency of a power amplifier is provided. The apparatus may include a power amplifier, and a variable impedance matching circuit coupled to the power amplifier to improve the transmitter efficiency over a range of output power. The variable impedance matching circuit may be adapted to match the output impedance of the power amplifier. The method may include varying the impedance of a circuit coupled to the output of a power amplifier during operation of the power amplifier to match the output impedance of the power amplifier.

High frequency power amplifier module, and wireless communication system

Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).

PWM-based DC-DC converter with assured dead time control exhibiting no shoot-through current and independent of type of FET used

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

N-way rf power amplifier with increased backoff power and power added efficiency

Abstract: An RF power amplifier for amplifying an RF signal over a broad range of power with improved efficiency includes a main amplifier (20) for amplifying an RF signal over a first range of power and with a power saturation level below the maximum of the broad range of power. A plurality of auxiliary amplifiers (21, 22, 23) are connected in parallel with the main amplifier (20) with each of the auxiliary amplifiers (21, 22, 23) being biased to sequentially provide an amplified output signal after the main amplifier (20) approaches saturation. The input signal is applied through a signal splitter (32) to the main amplifier (20) and the plurality of auxiliary amplifiers (21, 22, 23), and an output for receiving amplified output signals from the main amplifier (20) and the plurality of auxiliary amplifiers (21, 22, 23) includes a resistive load R/2. The split input signal is applied through a 90° transformer (30) to the main amplifier (20), and the outputs of the auxiliary amplifiers (21, 22, 23) are applied through 90° transformers (24, 25, 26) to a output load (28). When operating below saturation, the main amplifier (20) delivers power to a load of 2R and the main amplifier (20) delivers current to the load which is one-half the current at maximum power and the amplifier is saturated.

A Ka-band power amplifier based on a low-profile slotted-waveguide power-combining/dividing circuit

Abstract: In this paper, a Ka-band power amplifier based on a resonant slotted-waveguide-to-microstrip power-dividing/combining circuit is presented. The advantages of this structure are its low profile, ease of fabrication, as well as its potential for high power-combining efficiency. In addition, efficient heat sinking of monolithic microwave integrated circuit (MMIC) devices is achieved. A slotted-waveguide power amplifier using eight MMIC amplifiers was designed and fabricated. The measured power-combining efficiency at 33 GHz is 72%. In addition, simulation results predicting the performance degradation of the slotted-waveguide power amplifier due to multiple device failure are presented.

Current detecting circuit AC/DC flyback switching power supply

Abstract: A current detecting circuit connects to a secondary side of a transformer, including a first, second transistors and a field-effect transistor (FET). The first transistor has a base connecting with the base and emitter of the second transistor to form a common base terminal, an emitter forming a first detecting terminal and a collector forming a feedback terminal. The second transistor has a collector forming a second detecting terminal. The FET is used to replace a prior current rectifying diode. The FET has a source connecting to an output terminal of the transformer and a drain connecting to a direct current (DC) output terminal. The first, second detecting terminals and feedback terminal are connected with the source, drain and gate of the FET, respectively. Via detecting the current of the DC output terminal, the FET is timely turned on and off to release the energy stored in the transformer.

Mixed-mode (current-voltage) audio amplifier

Abstract: A method and system for providing a mixed-mode (current- and voltage-source) audio amplifier is disclosed. The mixed-mode amplifier includes a voltage sensing feedback path including a first network comprising at least one circuit; and a current sensing feedback path including a second network comprising at least one circuit. According to the method and system disclosed herein, the first and second networks vary an output impedance or transconductance of the amplifier as a function of frequency of the input voltage signal, such that at a first frequency range, the amplifier operates substantially as a current amplifier, and at a second frequency range, the amplifier operates substantially as a voltage amplifier, thereby inheriting distortion reduction of the current amplifier and stability of the voltage amplifier.

DC-coupled multi-stage amplifier using all-pass resistive/capacitive network for level shifting

Abstract: A resistive level-shifting biasing network is used with a capacitor in parallel to couple FET-based amplifier stages from DC to several GHz in a multi-stage amplifier. The output of the first amplifier stage is connected to the input of the second amplifier stage without a blocking capacitor or level-shifting diodes, allowing a portion of the drain current for the first amplifier stage to be supplied from the second amplifier stage. In a particular embodiment, a distributed amplifier achieved over 20 dB gain from DC to about 80 GHz using three traveling wave amplifier chips.

Highly linear RF CMOS amplifier and mixer adopting MOSFET transconductance linearization by multiple gated transistors

Abstract: A highly linear CMOS RF amplifier and mixer circuits adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel, combined with some additional circuit techniques such as cascode for amplifier and harmonic tuning for mixer, are reported. Experimental result designed using above techniques shows IP3 improvements at given power consumption by as large as 10 dB for RF amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and NF.

Input buffer amplifier with centroidal layout

Abstract: An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. Furthermore, FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry. The overall horizontal and vertical symmetry of the input buffer amplifier improves the device matching between differential signal paths. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly. The reduction in differential offset and common mode offset improves the linearity and dynamic range of input buffer amplifier. The improved differential matching also reduces signal distortion and the susceptibility to power supply noise.