Showing papers on "FET amplifier published in 2006"

The Doherty power amplifier

Abstract: In this article, we show that the Doherty amplifier is capable of delivering the stringent requirements of the base station power amplifiers. We explain the operation principles, including both linearity and efficiency improvements, and the basic circuit configuration of the amplifier. Advanced design methods to operate across wide bandwidth and improve the linearity are also described. For verification, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal. These results show that the Doherty amplifier is a promising candidate for base station power amplifiers with wide bandwidth, high efficiency, and linearity

Amplification with feedback capacitance for photodetector signals

Abstract: Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

Abstract: In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc

Multi-band low noise amplifier, multi-band low noise amplifier module, wireless integrated circuit and multi-band RF module

Abstract: A multi-band radio module for selectively supplying received signals in a plurality of frequency bands to a low noise amplifier via an input impedance matching circuit by switching over the operation mode of the low noise amplifier is comprised of: a pre-stage amplification unit including a plurality of fundamental amplifiers connected to one another in parallel, the fundamental amplifiers sharing a load impedance connected to a source voltage and a grounded degeneration impedance and having input signal lines commonly connected to an input impedance matching circuit; a post-stage amplifier to which the output signals of the plurality of fundamental amplifiers are commonly inputted; and a bias control unit for selectively turning on the fundamental amplifiers, wherein the input impedance of the low noise amplifier is selectively optimized for the matching circuit depending on the RF band to be received.

Amplifier mode switch

Abstract: A power amplifier includes a main amplifier having a first output. An auxiliary amplifier has a second output coupled to the first output. A splitter splits a RF input into a first input provided to the main amplifier and a second input delayed by one/quarter wavelength provided to the auxiliary amplifier. A bias control is coupled to the auxiliary amplifier for controllably switching operation of the power amplifier between two different modes of operation.

A 500W Push-Pull AlGaN/GaN HEMT Amplifier for L-Band High Power Application

Abstract: We have successfully developed a 500W AlGaN/GaN HEMT power amplifier with a frequency of 1.5GHz in L-Band, operating at 65V drain bias voltage. This amplifier consists of 4-chips of HEMT die developed for L-band frequency operation with push-pull configuration. The developed amplifier has an output power of 500W and a high linear gain of 17.8dB at the frequency of 1.5GHz under pulsed conditions at a duty of 10% with a pulse width of 100musec. To the best of our knowledge, this is the highest power ever reported for L-band GaN-related amplifier

Highly linear three-way Doherty amplifier with uneven power drive for repeater system

Abstract: We have demonstrated a high linear three-way Doherty amplifier by applying uneven power drive and optimizing the peaking biases and load impedances. The amplifier has been implemented at 2.14GHz using 190-W peak envelope power laterally diffused metal-oxide-semiconductor field-effect transistors. For comparison, a class AB biased amplifier is tested as it's counterpart. The two-tone signal and forward-link wideband code-division multiple access (WCDMA) signal have been selected as test signals. At 42dBm (12.5-dB backed-off output power), there are large improvements in the third- and fifth-order intermodulation distortions. For the forward-link four-carrier WCDMA signal, the adjacent channel leakage ratio (ACLR) performances at 5-MHz and 10-MHz offsets are -52.5dBc and -53.4dBc, respectively, and satisfy the generally medium high power amplifier linearity target without using any other linearization circuits. In comparison with the class AB amplifier, the three-way Doherty amplifier with uneven power drive has 9.8-dB lower ACLR at 5-MHz offset while maintaining a comparable drain efficiency of 10.2%.

Power amplifier for ultrasonic transducer excitation

Abstract: Design of the power amplifier for ultrasonic transducer excitation is presented. We assumed that the amplifier output impedance will be significantly lower than the transducer input impedance. Therefore we suggest using the transformer as voltage step-up and impedance matching element. The transformer influence on the ultrasonic transducer bandwidth and power transfer efficiency is analyzed using Butterworth-Van Dyke transducer model. The transformer magnetizing and leakage inductance influence on particular air coupled transducer are investigated by modelling and experimentally. The transformer application allows using the same carrier type (n-p-n bipolar or n-channel MOSFET) active elements in push-pull configuration at the amplifier output stage. The commercially available relatively low voltage MOSFET is suggested. Two types of MOSFET transistors are investigated. The resulting amplifier performance has been investigated. The 50kHz to 3MHz bandwidth is obtained for the suggested amplifier configuration. The distortion and efficiency performance are investigated experimentally and using the P-SPICE modelling over various input signals range. The total harmonic distortion of 4% using 3kW load and 400Vp-p 1MHz frequency signal is achieved. The investigation indicate the ability to use such a power amplifier for arbitrary waveform or high power continuous waveform excitation of the ultrasonic transducer.

Field effect transistor with independently biased gates

Abstract: A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance.

High frequency power amplifier, transmitter and mobile communication terminal using the power amplifier

Abstract: A high frequency power amplifier maintains an excellent linearity regardless of a fluctuation of a load impedance and is downsized. The high frequency power amplifier detects an AC voltage amplitude at an output terminal of a final amplification stage transistor, and suppresses an input signal amplitude of a power amplifier when the voltage amplitude exceeds a predetermined threshold value.

100 W C-band single-chip GaN FET power amplifier

Abstract: A single-chip GaN-FET amplifier exhibits record output powers of C-band solid-state amplifiers under continuous-wave (CW) and pulsed operation conditions. At 5.0 GHz, the developed GaN-FET amplifier with 24 mm gate periphery delivered a CW 100 W output power with 12.9 dB linear gain and 31% power-added efficiency and a pulsed 155 W output power with 13.0 dB linear gain.

Amplifier offset cancellation devices, systems, and methods

Abstract: Methods, devices, and systems for offset cancellation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of pixel columns coupled in parallel. During a cancellation phase, an amplifier offset may be canceled by selectively coupling a first amplifier output to a first amplifier input and a second amplifier output to a second amplifier input. During a portion of the cancellation phase, a buffer may use the first amplifier input to drive a first pixel signal. During a different portion of the cancellation phase, the buffer may use the second amplifier input to drive a second pixel signal. To sense the pixel columns during an amplification phase, the first and second pixel signals are coupled to the first and second amplifier inputs, respectively, with the result that the amplifier offset and the buffer offset are cancelled from the amplifier output.

Design Guidelines for a Novel Tapered Drain Line Distributed Power Amplifier

Abstract: In this paper, the analysis, design, and measured results of a novel tapered drain line distributed power amplifier are presented. The prototype tapered drain line distributed power amplifier has a gain of 10 dB, power-added-efficiency of about 24%, and output power of about 18dBm, over a 4.5 GHz bandwidth. The drain line impedance tapering technique is shown to significantly increase the efficiency and output power of a distributed amplifier. The topology of the tapered drain line distributed power amplifier is suitable for monolithic implementation.

System and method for driving a power field-effect transistor (FET)

Abstract: A system and method are provided for driving a power field-effect transistor (FET). In one embodiment, a system comprises a control circuit (54) that generates a control signal (56) to provide a gate voltage of the power FET. The system further comprises a slope control circuit (62) coupled between the control circuit and the power FET that is operative to dynamically control the rate-of-change of a gate voltage of the power FET to reduce electro-magnetic interference (EMI) emissions and power loss resulting from switching the power FET.

A Novel Tunable Transconductance Amplifier Based on Voltage-Controlled Resistance by MOS Transistors

Abstract: A new tunable transconductance amplifier is proposed for the programmable analog signal processing or low power filter applications. The transconductor linearization is based on the compensation of nonlinear behaviour by two MOS transistors. The transconductance amplifier in this brief exhibits the good common-mode dynamic range and the voltage-controlled transconductance. HSPICE circuit simulation using 0.18-mum standard CMOS technology shows the plusmn50% tunable transconductance range with the plusmn0.2-V control voltage, and the linearity of less than 60 dB in the total harmonic distortion for the 0.6 VPP input signal

Cascode connection circuit

Abstract: A cascode connection circuit includes a first field effect transistor (FET) which has a source terminal and a drain terminal, the source terminal being connected to ground; a second FET which has a source terminal and a gate terminal, the source terminal being connected to the drain terminal of the first FET; and a first resistor and a first capacitor connected in series between the source terminal of the first FET and the gate terminal of the second FET. The first FET and the second FET are cascode-connected to each other. The product of the resistance of the first resistor and the capacitance of the first capacitor does not exceed 0.1 times the period of an operating frequency of the circuit.

Step-up converter

Abstract: A step-up converter includes an inductor which receives input voltage Vi at one end, a first FET of the first conduction type which functions as a switch for determining whether or not energy is accumulated in the inductor, a second FET of the second conduction type which rectifies a current output from the other end of the inductor, an output capacitor having an end connected to the source of the second FET, a current detection circuit, and a feedback control circuit. The current detection circuit detects a current flowing through the first N-channel FET to output current detection signal Vc. The feedback control circuit controls the operations of the first N-channel FET and a P-channel FET based on current detection signal Vc.

Apparatus and method for adaptive biasing of a Doherty amplifier

Abstract: An apparatus and method for adaptive biasing of a Doherty amplifier (102) is disclosed. The apparatus includes a carrier amplifier (210), a peaking amplifier (214), a carrier amplifier bias circuit (208) and a peaking amplifier bias circuit (212), all integrated onto a single chip. The method includes dividing an input signal into an in-phase signal and a quadrature phase signal. The method further includes sampling the input signal and applying the sampled signal to the biasing circuits. The method further includes adaptively biasing the carrier amplifier and the peaking amplifier by the output of the biasing circuits.

Equivalent circuit for an organic field-effect transistor from impedance measurements under dc bias

Abstract: The output and forward transfer impedance of an organic field-effect transistor have been measured by a lock-in amplifier technique. The small-signal ac response of a pentacene FET, under dc bias, is used to construct the equivalent circuit. The output impedance parameters are numerically simulated using Bode plot analysis and the deviations at low frequency are modeled with contact impedance of the source-drain channel. The ac current generator at the output is estimated along with the gate capacitances.

Amplifiers with compensation

Abstract: An amplifier system includes a first amplifier stage having an input and an output. A second amplifier stage has an input and an output, the input of the second amplifier stage being connected to the output of the first amplifier stage. A transistor has a control terminal, a first terminal, and a second terminal, the first terminal of the transistor being coupled to the output of the first amplifier stage and the input of the second amplifier stage. A first capacitance has a first terminal and a second terminal, the first terminal of the first capacitance being connected to the input of the first amplifier stage, the second terminal of the first capacitance being connected to the second terminal of the transistor. A first current source to source current to amplifier system, the first current source being is connected to the output of the first amplifier stage. A second current source will sink current from the amplifier system. The second current source is connected to the second terminal of the first capacitance and the second terminal of the transistor.

Displaced electrode amplifier

Abstract: A displaced electrode amplifier ('DEA') for measuring signals from high impedance sources. The amplifier may include an operational amplifier ('op-amp') configured as a unity gain buffer, with a feedback path to the non-inverting input to at least partly compensate for a parasitic input shunt impedance. In cases where the device is to measure AC signals in high ambient temperatures, the non-inverting input may be coupled via a large resistance to a ground reference that is driven with a second feedback signal to magnify the effective value of the large resistance. Where a differential configuration is desired, one or more tuning resistors may be provided to match responses of different input buffer stages, thereby maximizing the common mode rejection. The disclosed amplifier is suitable for use in oil-based mud resistivity imaging tools, but is also suitable for other applications.

InAs HEMT narrowband amplifier with ultra-low power dissipation

Abstract: The design, fabrication and performance of a prototype narrowband amplifier using InAs-channel HEMTs are reported. The amplifier, which is realised on an RT/Duroid circuit board with a combination of transmission lines and lumped components, is intended for a long-life battery-powered application. The two-stage amplifier has 20 dB of gain with a bandwidth of 4% in S-band and dissipates a total power of only 365 /spl mu/W.

Solid-state image-pickup device with column-line amplifiers and limiter

Abstract: The levels of the power supply and the ground are kept constant against a parasitic resistance by keeping the constant current of an amplifier irrespective of the size of a pixel signal and the gain of the amplifier in this case in an image signal reading circuit system having the amplifier arranged to each column. The amplifier has a limiter at an output terminal thereof which limits an output voltage of the amplifier to a range for keeping the constant consumption-current.

High power doherty amplifier using multi-stage modules

Abstract: A high power Doherty RF amplifier utilizes multi-stage amplifier modules for both the main amplifier and the peak amplifiers. In one embodiment of a two way two stage amplifier, the first stage of each amplifier module can include signal pre-distortion whereby the first stage compensates for distortion in both the first and second stages. The design is simple and results in a high efficiency amplifier with high gain. In one embodiment, a commercially available CREE PFM19030SM power module is used in both the main amplifier and the peak amplifier.

Doherty power amplifier with phase compensation

Abstract: A Doherty power amplifier (300) is provided that includes a main amplifier device (302) and an auxiliary amplifier device (304). The Doherty power amplifier further includes a phase compensation network (320a and/or 320m). The phase compensation network is configured to maintain a substantially constant phase of one of an output signal from the main amplifier device or an output signal from the auxiliary amplifier device across a range of input powers. The Doherty power amplifier further includes an impedance inverter (106) for power combining an output signal of the main amplifier device with an output signal of the auxiliary amplifier device.

370-W Output Power GaN-FET Amplifier with Low Distortion for W-CDMA Base Stations

Abstract: High output power and low intermodulation distortion (IMD) GaN-FET amplifiers are highly sought after for W-CDMA base stations. In order to obtain high output power, we have developed a field-modulating plate GaN-FET with a high maximum drain current and a high gate-to-drain breakdown voltage. Also, in order to suppress the memory effects that obstruct digital predistortion (DPD) linearization in W-CDMA power amplifiers, we have newly developed the bias network, in which frequency-dependent impedance at the base band of multi-carrier W-CDMA signals is reduced. As a result, the GaN-FET amplifier developed for W-CDMA base stations achieves a record 370-W W-CDMA peak output power, and a low DPD linearized IMD of less than -50 dBc at the highest W-CDMA average output power of over 60 W, resulting in a significant improvement of DPD linearization not only in IM3 but also in IMS and IM7

Load modulation power amplifier with lumped-element combiner for IEEE 802.11b/g WLAN applications

Abstract: A new monolithic microwave integrated circuit power amplifier for 802.11b/g wireless local area network (WLAN) has been implemented using the load modulation concept of a Doherty amplifier. The /spl lambda//4 transmission line for the load modulation circuit of the carrier amplifier is replaced by a lumped element based /spl pi/-network, which dual functions as an output matching network, simultaneously. This amplifier shows that error vector magnitude is about 4.6% and power added efficiency (PAE) about 31.8% at P/sub out/ of 19 dBm for a 802.11g 64QAM signal. PAE of the power amplifier is about 49.6%, and adjacent channel leakage ratio below 37.2dBc at 11 MHz offset at P/sub out/ of 23 dBm for the 802.11b complementary code keying signal

Mosfet with temperature sense facility

Abstract: A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.

Current mirror circuit having drain-source voltage clamp

Abstract: A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output current and further includes maintaining a voltage across the output transistor. One embodiment includes conducting a reference current through a diode-coupled first field-effect transistor (FET) and biasing a gate of a second FET matched to the diode-coupled first FET by a voltage equal to a gate voltage of the diode-coupled first FET. A current equal to the reference current is conducted through a third FET having a gate coupled to a drain of the second FET, the third FET matched to the second FET.