Showing papers on "FET amplifier published in 2007"

An Energy-Efficient Micropower Neural Recording Amplifier

Abstract: This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier

Abstract: A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm2 die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%.

Transmit/receive switch

Abstract: A radio frequency (RF) transmit/receive switch. The transmit/receive switch comprises an impedance matching circuit and a voltage scaling circuit. The impedance matching circuit matches an incoming RF signal to a low noise amplifier and an outgoing RF signal from a power amplifier. The voltage scaling circuit, coupled to the impedance matching circuit, the power amplifier, and the low noise amplifier, attenuates the outgoing RF signal to a scaled signal within a breakdown voltage of a transistor device in the low noise amplifier during transmission of the outgoing RF signal.

Highly efficient series string LED driver with individual LED control

Abstract: A current source generates, with high efficiency, a current that is substantially constant over a wide range of output voltages. This current is injected into the first end of a series-connected string of LEDs, with the second end of the string connected through a resistor to ground. The voltage developed across this resistor, which is a measure of current flow in the series string, is fed back to the current source, wherein feedback maintains nearly constant current output over a wide range of output voltages. A field effect transistor (FET) is placed in parallel with each LED in the string. A level shift gate driver couples a pulse width modulated control signal to the gate of each FET. With the FET being coupled across a particular LED, the LED can be bypassed when the FET is actuated or receive current when the FET is deactuated. By modulating the duty cycle of each FET, the brightness of each associated LED may be varied smoothly over its full range.

Chopper-stabilized instrumentation amplifier for impedance measurement

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Sense amplifier circuit having current mirror architecture

Abstract: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

Chopper-stabilized instrumentation amplifier

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Design of H-Bridge Class-D Power Amplifiers for Digital Pulse Modulation Transmitters

Abstract: This paper presents an H-bridge class-D power amplifier (PA) for digital pulse modulation transmitters. The class-D amplifier can be driven by two-or three-level digital signals generated by a delta-sigma modulator (DSM) and provides a linear microwave output after filtering. Within the amplifier, the pull-up and pull-down devices are driven separately to improve the amplifier efficiency by minimizing the loss associated with shoot-through current. The H-bridge class-D PA system was tested with code-division multiple-access IS-95 signals at 800 MHz. Using binary DSM signals, a drain efficiency of 31% was achieved with an output power of 15 dBm and an adjacent channel power ratio of -43 dBc. With three-level DSM signals, a drain efficiency of 33% was achieved at same output power. An analysis of the factors governing amplifier efficiency is provided.

A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

Abstract: This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .

Notch filter for ripple reduction in chopper stabilized amplifiers

Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier (2) having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter (15) will filter the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

Microelectronics : circuit analysis and design

Abstract: Microelectronics: Circuit Analysis and Design Prologue I: Prologue to Electronics Brief History Passive and Active Devices Electronic Circuits Discrete and Integrated Circuits Analog and Digital Signals Notation Summary Part I: Semiconductor Devices and Basic Applications Chapter 1: Semiconductor Materials and Diodes 1.0 Preview 1.1 Semiconductor Materials and Properties 1.2 The pn Junction 1.3 Diode Circuits: DC Analysis and Models 1.4 Diode Circuits: AC Equivalent Circuit 1.5 Other Diode Types 1.6 Design Application 1.7 Summary Problems Chapter 2: Diode Circuits 2.0 Preview 2.1 Rectifier Circuits 2.2 Zener Diode Circuits 2.3 Clipper and Clamper Circuits 2.4 Multiple Diode Circuits 2.5 Photodiode and LED Circuits 2.6 Summary Problems Chapter 3: The Field-Effect Transistor 3.0 Preview 3.1 Basic Bipolar Junction Transistor 3.2 DC Analysis of Transistor Circuits 3.3 Basic Transistor Applications 3.4 Bipolar Transistor Biasing 3.5 Multistage Circuits 3.6 Design Application 3.7 Summary Problems Chapter 4: Basic FET Amplifiers 4.0 Preview 4.1 Analog Signals and Linear Amplifiers 4.2 The Bipolar Linear Amplifier 4.3 Basic Transistor Amplifier Configurations 4.4 Common-Emitter Amplifiers 4.5 AC Load Line Analysis 4.6 Common-Collector (Emitter-Follower) Amplifier 4.7 Common-Base Amplifier 4.8 The Three Basic Amplifiers: Summary and Comparison 4.9 Multistage Amplifiers 4.10 Power Considerations 4.11 Design Application 4.12 Summary Problems Chapter 5: Bipolar Junction Transistor 5.0 Preview 5.1 MOS Field-Effect Transistor 5.2 MOSFET DC Circuit Analysis 5.3 Basic MOSFET Applications: Switch, Digital Logic Gate, and Amplifier 5.4 Constant Current Biasing 5.5 Multistage MOSFET Circuits 5.6 Junction Field-Effect Transistors 5.7 Design Application 5.8 Summary Problems Chapter 6: Basic BJT Amplifiers 6.0 Preview 6.1 The MOSFET Amplifier 6.2 Basic Transistor Amplifier Configurations 6.3 The Common-Source Amplifier 6.4 The Source-Follower Amplifier 6.5 The Common-Gate Amplifier 6.6 The Three Basic Amplifier Configurations: Summary and Comparison 6.7 Single-Stage Integrated Circuit MOSFET Amplifiers 6.8 Multistage Amplifiers 6.9 Basic JFET Amplifiers 6.10 Summary Problems Chapter 7: Frequency Response 7.0 Preview 7.1 Amplifier Frequency Response 7.2 System Transfer Functions 7.3 Frequency Response: Transistor Amplifiers with Circuit Capacitors 7.4 Frequency Response: Bipolar Transistor 7.5 Frequency Response: The FET 7.6 High-Frequency Response Transistor Circuits 7.7 Summary Problems Chapter 8: Output Stages and Power Amplifiers 8.0 Preview 8.1 Power Amplifiers 8.2 Power Transistors 8.3 Classes of Amplifiers 8.4 Class-A Power Amplifier 8.5 Class-AB Push-Pull Complementary Output Stages 8.6 Summary Problems Prologue II: Prologue to Electronic Design Preview Design Approach System Design Electronic Design Conclusion Part II: Analog Electronics Chapter 9: Ideal Operational Amplifiers and Op-Amp Circuits 9.0 Preview 9.1 The Operational Amplifier 9.2 Inverting Amplifier 9.3 Summing Amplifier 9.4 Noninverting Amplifier 9.5 Op-Amp Applications 9.6 Operational Transconductance Amplifiers 9.7 Op-Amp Circuit Design 9.8 Design Application 9.9 Summary Problems Chapter 10: Integrated Circuit Biasing and Active Loads 10.0 Preview 10.1 Bipolar Transistor Current Sources 10.2 FET Current Sources 10.3 Circuits and Active Loads 10.4 Small-Signal Analysis: Active Load Circuits 10.5 Summary Problems Chapter 11: Differential and Multistage Amplifiers 11.0 Preview 11.1 The Differential Amplifier 11.2 Basic BJT Differential Pair 11.3 Basic FET Differential Pair 11.4 Differential Amplifier with Active Load 11.5 BiCMOS Circuits 11.6 Gain Stage and Simple Output Stage 11.7 Simplified BJT Operational Amplifier Stage 11.8 Diff-Amp Frequency Response 11.9 Summary Problems Chapter 12: Feedback and Stability 12.0 Preview 12.1 Introduction to Feedback 12.2 Basic BJT Differential Pair 12.3 Basic FET Differential Pair 12.4 Voltage (Series-Shunt) Amplifier 12.5 Current (Shunt-Series) Amplifier 12.6 Transconductance (Series-Series) Amplifier 12.7 Transresistance (Shunt-Shunt) Amplifier 12.8 Loop Gain 12.9 Stability of the Feedback Circuit 12.10 Frequency Compensation 12.11 Summary Problems Chapter 13: Operational Amplifier Circuits 13.0 Preview 13.1 General Op-Amp Design 13.2 A Bipolar Operational Amplifier Circuit 13.3 CMOS Operational Amplifier Circuits 13.4 BiCMOS Operational Amplifier Circuits 13.5 JFET Operational Amplifier Circuits 13.6 Summary Problems Chapter 14: Nonideal Effects in Operational Amplifier Circuits 14.0 Preview 14.1 Practical Op-Amp Parameters 14.2 Finite Open-Loop Gain 14.3 Frequency Response 14.4 Offset Voltage 14.5 Input Bias Current 14.6 Additional Nonideal Effects 14.7 Summary Problems Chapter 15: Applications and Design of Integrated Circuits 15.0 Preview 15.1 Active Filters 15.2 Oscillators 15.3 Schmitt Trigger Circuits 15.4 Nonsinusoidal Oscillators and Timing Circuits 15.5 Integrated Circuit Power Amplifiers 15.6 Voltage Regulators 15.7 Summary Problems Prologue III: Prologue to Digital Electronics Introduction Logic Functions and Logic Gates Logic Levels Noise Margin Propagation Delay Times and Switching Times Summary Part III: Digital Electronics Chapter 16: MOSFET Digital Circuits 16.0 Preview 16.1 NMOS Inverters 16.2 NMOS Logic Circuits 16.3 CMOS Inverter 16.4 CMOS Logic Circuits 16.5 Clocked CMOS Logic Circuits 16.6 Transmission Gates 16.7 Sequential Logic Circuits 16.8 Memories: Classification and Architectures 16.9 RAM Memory Cells 16.10 Read-Only Memory 16.11 D/A Converters 16.12 A/D Converters 16.13 Summary Problems Chapter 17: Bipolar Digital Circuits 17.0 Preview 17.1 Emitter-Coupled Logic (ECL) 17.2 Modified ECL Circuit Configurations 17.3 Schottky Transistor-Transistor Logic 17.4 BiCMOS Digital Circuits 17.5 Summary Problems Appendices

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

Abstract: This paper reports on the design methodology and experimental characterization of the inverse class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-mm gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieve a peak power-added efficiency of 64% and drain efficiency of 69%, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

Design of a High-Efficiency and High-Power Inverted Doherty Amplifier

Abstract: In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

A 38–46 GHz MMIC Doherty Power Amplifier Using Post-Distortion Linearization

Abstract: This letter describes the first demonstration of a fully integrated Doherty power amplifier (PA) monolithic microwave integrated circuit (MMIC) with post-distortion linearization at millimeter-wave (MMW) frequency band. The Doherty amplifier MMIC, using a 0.15-mum GaAs HEMT process, achieves a small signal gain of 7dB from 38 to 46GHz with a compact chip size of 2mm2. The saturation output power of the Doherty amplifier is 21.8dBm. The similar topology between the Doherty amplifier and post-distortion linearization makes it possible to improve efficiency and linearity simultaneously in MMW PA designs. After gate bias optimization of the main and peaking amplifier, the drain efficiency improved 6% at 6-dB output back-off and the inter-modulation distortion (IMD) of quasi Doherty amplifier can be improved 18dB at 42GHz compared with the balanced amplifier operation

Higher-order plasmon resonances in gan-based field-effect transistor arrays

Abstract: Terahertz (THz) response spectra of GaN-based field-effect transistor (FET) arrays are calculated in a self-consistent electromagmetic approach. Two types of FET arrays are considered: (i) FET array with a common channel and a large-area grating gate, and (ii) array of FET units with separate channels and combined intrinsic source and drain contacts. It is shown that the coupling between plasmons and THz radiation in the FET array can be strongly enhanced as compared to a single-unit FET. The computer simulations show that the higher-order plasmon modes can be excited much more effectively in the array of FET units with separate channels and combined source and drain contacts then in FET array with a common channel and a large-area grating gate.

Power amplifier matching circuit and method using tunable mems devices

Abstract: The present disclosure relates to a power amplifier circuit. In one example, the power amplifier circuit includes a power amplifier coupled to a variable load and a digitally tunable impedance matching network (TMN) positioned between the power amplifier and the variable load. The TMN includes at least one controllable capacitor having a maximum capacitance CT, where the controllable capacitor has a plurality of actuable capacitive elements having differing reactance values ranging from CT*2 0 to CT*2 N , where N=>1.

Multiple power mode amplifier with bias modulation option and without bypass switches

Abstract: A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in radio frequency (RF) applications such as mobile telephones, pagers, portable digital assistants, and wireless e-mail devices. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units (130, 140, 150, and 160), impedance transformer (170), and a power stage (120). An implementation provides further power consumption savings by modulating a bias of an amplifier stage.

Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration

Abstract: The stacked-device power-combining technique is a proven method to increase the output power and load impedance of a power amplifier (PA) simultaneously. The series-input configuration is physically realizable for multicell stacked device configuration in monolithic circuits. The series-input and series-output stack configuration is rigorously analyzed and proven to increase both the input impedance and output impedance simultaneously, easing the matching circuit designs in high PAs. The effects of asymmetry of the input feed and amplifier cells due to distributed effects and process variation on the performance of the stack amplifier are discussed. A four-cell HBT amplifier operating at 5-6 GHz is demonstrated to validate the circuit concept.

Method and system for software defined power amplifier for multi-band applications

Abstract: Methods and systems for software definition of a power amplifier for multi-band applications are disclosed and may comprise configuring a single programmable output stage of a transmitter to transmit a signal via one of a plurality of selectively coupled antennas, wherein each antenna handles signals in a different frequency band. A power amplifier within the single programmable output stage may be tuned to a frequency within a range of frequencies handled by the selectively coupled antenna. The tuning may be accomplished by programmably adjusting at least one inductance and capacitance. The antennas may be impedance matched to the power amplifier using transformers and may be activated by at least one integrated transistor. The power amplifier may be biased in a class of operation, which may include Class A, AB, C and F, and may be biased utilizing a digitally-controlled current source and a digitally-controlled voltage source.

Enhanced doherty amplifier with asymmetrical semiconductors

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Sensitivity Characteristics of Inverse Class-E Power Amplifier

Abstract: In this paper, an analysis is performed in order to determine the effects that variations in circuit component values, frequency, and duty cycle have on the performance of the newly introduced inverse Class-E amplifier. Analysis of the inverse Class-E amplifier under the generalized condition of arbitrary duty cycle is performed and it is shown that the inverse Class-E amplifier is reasonably tolerant to circuit parameter variations. When compared to the conventional Class-E amplifier the inverse Class-E amplifier offers the potential for high efficiency at increased output power as well as higher peak output power levels than are available with a conventional Class-E amplifier. Further the inverse Class-E amplifier provides more flexibility for deployment with a pulsewidth modulator as the means of producing full-carrier amplitude modulation (AM) due to its ability to operate to high AM modulation indices

Chopper-stabilized instrumentation amplifier for wireless telemetry

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device. The amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications.

Low-noise amplifier

Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.

Ultra low output impedance rf power amplifier for parallel excitation

Abstract: An ultra low output impedance RF power amplifier for driving a multiple transmit coil Magnetic Resonance Imaging (MRI) system is described, comprising an output matching network with high power MOSFET operatively coupled to at least one transmit coil in the MRI system for a desired output power and impedance. This invention also describes a method for achieving decoupling using the RF power amplifier to drive at least one transmit coil.

Advanced Design of Linear Doherty Amplifier for High Efficiency using Saturation Amplifier

Abstract: We have developed a saturation Doherty amplifier which has higher efficiency than the conventional or linear Doherty amplifier. The proposed Doherty amplifier is based on the saturation amplifiers with the harmonic control circuit. We have analyzed the efficiency and the saturation operation of the amplifier related to the load modulation. To interpret the saturation operation according to the power level and harmonic cancellation mechanism, we have simulated the voltage and current waveforms and the IM3 amplitudes and phases of the carrier and peaking amplifiers. For verification, we have implemented the saturation Doherty power amplifier with inverse class F harmonic control circuit using Freescale MRF281SR1 LDMOSFET with a 4-W peak envelope power (PEP). For a 1-GHz forward-link WCDMA signal, the measured drain efficiency of the amplifier is 54.7%, and the measured adjacent channel leakage ratio (ACLR) is -29.4 dBc at an average output power of 32 dBm, while those of the comparable the inverse class F amplifier are 38.7% and -21.4 dBc at the same average output power level, respectively.

50% Drain Efficiency Doherty Amplifier with Optimized Power Range for W-CDMA Signal

Abstract: A novel high-efficiency Doherty amplifier is presented. A carrier amplifier and a peak amplifier in the Doherty amplifier are set to asymmetrical drain voltages to extend the power range where a high drain efficiency of the Doherty amplifier is maintained. Matching circuits of the carrier amplifier and the peak amplifier are designed for each drain voltage so that the drain efficiency and signal linearity of the Doherty amplifier at a 9 dB backoff point from its saturated output power (Psat) become higher than those of a conventional Doherty amplifier. These simple steps optimize the power range of the Doherty amplifier for a wideband code-division multiple-access (W-CDMA) signal that has a peak-to-average power ratio (PAR) of 9 dB. A Doherty amplifier containing gallium nitride (GaN) high-electron-mobility transistors (HEMTs) achieves an adjacent channel leakage power ratio (ACLR) of -38 dBc and a drain efficiency of 50% at an output power of 45 dBm. This is the highest drain efficiency of a Doherty amplifier for a W-CDMA signal to the best of the authors' knowledge.

Load-Pull Analysis of Outphasing Class-E Power Amplifier

Abstract: In this paper, we discuss a load-pull analysis technique to charaterize the efficiency performance of class-E amplifier in an outphasing power combining scheme. Class-E amplifier has the potential to deliver high efficiency. Class-E amplifier is not an ideal current or voltage source as is required for the traditional analysis of outphasing structures. It requires a phase modulated input signal and has a non-linear transfer characteristic which is a function of load impedance. Here we define an operating load locus based on the load-pull analysis which can be used to predict the non-linear transfer function, efficiency, output power, input drive phase and many other factors associated with the outphasing class-E amplifier. This scheme could also be used to characterize any amplifier class in an outphasing structure.

Demonstration of a 270-GHz MMIC Amplifier Using 35-nm InP HEMT Technology

Abstract: In this letter, the first 270-GHz millimeter-wave integrated circuit (MMIC) amplifier is demonstrated. Peak measured gain of 11.6-dB is measured for the three stage amplifier realized in coplanar waveguide. Further, positive S21 gain is measured to 340GHz making this the highest frequency MMIC amplifier reported to date. The high frequency circuit performance is enabled through a 35-nm InP high electron mobility transistor capable of extremely high frequency operation

Multiband doherty amplifier

Abstract: A multiband Doherty amplifier having a configuration including a divider which divides an input signal into two, a carrier amplifier which amplifies one of the divided signals, a delay element which delays the other divided signal, a peak amplifier which amplifies the output signal of the delay element, an impedance converter which is connected to an output port of the carrier amplifier and performs predetermined impedance conversion and a combiner which combines the output signals of the peak amplifier and the impedance converter, wherein the electric length of the delay element is the same as the electric length of the impedance converter and the impedance converter has N (N≧2) cascade-connected impedance conversion transmission lines and performs substantially the same impedance conversion at each of the N frequencies.

Dynamic bias control in power amplifier

Abstract: An RF output power amplifier (PA) of a cellular telephone includes first and second Class AB amplifier circuits. If the cellular telephone is to operate in a high power operating mode, then the first amplifier drives the PA output terminal. The power transistor(s) in the first amplifier is/are biased at a first DC current and a first DC voltage so as to optimize efficiency and linearity at high output powers. If the cellular telephone is to operate in a low power operating mode, then the second amplifier drives the output terminal. The power transistor(s) in the second amplifier is/are biased at a second DC current and a second DC voltage so as to optimize efficiency and linearity at low output powers. By sizing the power transistors in the amplifiers appropriately, emitter current densities are maintained substantially equal so that PA power gain is the same in the two operating modes.