Showing papers on "FET amplifier published in 2011"

Monolithic semiconductor switches and method for manufacturing

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

Abstract: A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450x500 im² including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.

High power fet switch

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.

High-efficiency concurrent dual-band class-F and inverse class-F power amplifier

Abstract: A high-efficiency concurrent dual-mode dual-band power amplifier is presented. It simultaneously operates at class-F mode for one band and at inverse class-F mode for the other band. With this mode assignment method, the conflict in harmonic impedance control for concurrent dual-band applications is avoided. Experimental results show a high performance of more than 80% peaking power added efficiency with 40.6 and 41.8 dBm output power in the sampled bands of 0.8 and 1.25 GHz, respectively.

True Filterless Class-D Audio Amplifier

Abstract: The design of a fully integrated, filterless, class-D audio amplifier in standard 0.25- CMOS technology is described: a novel class-D amplifier architecture, where uniform pulsewidth modulation is introduced. The architecture attenuates residual clock signals around the loop allowing very low harmonic distortion, , to be achieved in conjunction with high PSRR, at 217 Hz. When driving 1.2 W into an 8- load, it achieves an SNR of 103 dB (A-weighted) with an efficiency of . The maximum output power at 1% THD is 3.1 W. Figures of merit are defined to establish that the amplifier exceeds the performance of alternative designs. The amplifier occupied a chip area 1.44 and was packaged as a WLCSP.

Radio Frequency Integrated Circuit

Abstract: Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: an internal input impedance matching topology in which the respective low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from said internal input impedance matching topology.

FET Modeling for Circuit Simulation

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High efficiency balanced output amplifier system

Abstract: A high efficiency amplifier system may include multiple output stages cooperatively operating to produce an amplified output signal. The amplifier system may be used in an audio system. The amplifier system may include a non-switchmode amplifier stage cooperatively operating with a switchmode amplifier stage to generate the amplifier output signal. The non-switchmode amplifier stage may selectively enable and disable the switchmode amplifier stage to optimize efficient operation. In addition, the switchmode amplifier stage may include multiple switching stages operated with interleave. The switching stages may be controlled to balance current output of the respective switching stages based on a measured current flow in at least one of the switching stages.

High efficiency envelope tracking power amplifier with very low quiescent power for 20 MHz LTE

Abstract: A high efficiency wideband envelope tracking power amplifier with low quiescent power is presented. The CMOS envelope amplifier has a combined linear amplifier and switching amplifier to achieve high efficiency and wider bandwidth. Quiescent power of the envelope amplifier is reduced using a source cross-coupled linear amplifier with inherently low DC power dissipation. Measurements show a power added efficiency of 45% for the envelope tracking power amplifier for 20 MHz LTE signal with 6.0 dB PAPR at 2.5 GHz at 1W output power.

A 67% PAE, 100 W GaN power amplifier with on-chip harmonic tuning circuits for C-band space applications

Abstract: This paper describes a high efficiency and high output power GaN power amplifier for C-band space applications. The amplifier uses on-chip harmonic tuned FETs to improve dc-to-rf conversion efficiency. A 2nd harmonic input tuning circuit is incorporated into each unit on-chip FET cell and realizes high precise control of 2nd harmonic input impedance. In addition, 2nd and 3rd harmonic output impedances are optimized with external output matching circuits. A 100 W power amplifier with 4-chips achieves a 67.0% PAE (72.4% drain efficiency) at 3.7 GHz under CW operating conditions. To the best of our knowledge, this is the highest efficiency of C-band power amplifiers ever reported with over 100 W output power.

III-nitride transistor stacked with FET in a package

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

L-band carbon nanotube transistor amplifier

Abstract: The first carbon nanotube transistor (CNT)-based single-stage L-band RF amplifier has been designed, built and characterised. The on-wafer probe measured data was used to design a single-stage discrete feedback amplifier with a CN FET die. The amplifier achieved 11 dB linear gain with better than 10 dB input/output return loss at 1.3 GHz. The measurement results match well with the simulation.

A Three Stage, Fully Differential 128–157 GHz CMOS Amplifier with Wide Band Matching

Abstract: A fully differential amplifier has been realized in 65 nm CMOS technology, which has demonstrated 20 dB peak gain, over 10 dB gain from 128-157 GHz, and 40 GHz positive gain range from 126 to 166 GHz. By using cascode architecture with high bulk voltage tied to the cascode devices in deep-Nwell, the amplifier ensures stability and can use 2 V supply reliably. By inserting a π-matching network between cascode devices, it broadens the amplifier working range. This amplifier occupies 0.05 mm2 chip area, delivers over 5 dBm output power, and consumes 51 mA from a 2 V supply. To the authors' best knowledge, this amplifier achieves the highest gain for CMOS amplifier beyond 100 GHz.

Low-Noise Parametric Resonant Amplifier

Abstract: We propose a resonant parametric amplifier with an enhanced noise performance by exploiting the noise-squeezing effect. Noise squeezing occurs through the phase-sensitive amplification process and suppresses one of the two quadrature components of the input noise. When the input signal is only in the direction of the nonsuppressed quadrature component, squeezing can lower that noise figure by almost 3 dB. The resonant structure of the proposed amplifier is inspired by a Fabry-Perot laser amplifier to achieve the squeezing effect using a low number of LC elements. We design and simulate the proposed noise-squeezing parametric amplifier in a conventional 65-nm CMOS process. A minimum noise-squeezing factor of -0.35 dB is achieved with a signal gain of 26 dB for one quadrature component of a 10-GHz narrow-band signal.

Doherty amplifier circuit

Abstract: The present invention relates to an amplifier (400, 500) comprising a plurality of Doherty amplifier cells (300a, 300b, 300c), each Doherty amplifier cell (300) comprising an input (302) and an output (304) respectively connected to an input (402, 502) and an output (404, 504) of the amplifier (400, 500), a main amplifier stage (308), a peak amplifier stage (311) and a signal combining circuit (313) configured to combine signals from outputs (309, 312) of the main (308) and peak (311) amplifiers and provide a combined signal to the output (304) of the Doherty amplifier cell (300). Each cell comprises a controllable splitter (318) having an input (317) connected to the input (302) of the Doherty amplifier cell (300). The controllable splitter (318) is configured to receive a splitter control signal and modify an amplitude and phase of a signal at the input (302) of the Doherty amplifier cell (300) in response to the splitter control signal and to provide a first modified signal to the input (307) of the main amplifier stage (308) and a second modified signal to the input (310) of the peak amplifier stage (311).

Broadband Differential Low-Noise Amplifier for Active Differential Arrays

Abstract: In this paper, differential low-noise amplifiers are presented as a very powerful solution for radio astronomy applications. A fully differential amplifier topology has been analyzed and implemented in microstrip technology with discrete surface mount components. The amplifier design is made for an active receiving dense antenna array. Thus, the differential amplifier source impedance is no longer 50 Ω, but 150 Ω from the proposed bunny-ear antennas. A full characterization in terms of gain and noise has been undertaken. Source-pull measurements have been included in order to evaluate the performance of the amplifiers operating with variable source impedances. Noise temperatures below 55 K have been obtained for the differential design in the 300-1000-MHz band for the 150-Ω impedance. In addition, the results for different scanning angles are also presented.

Cryogenic ultra-low-noise SiGe transistor amplifier

Abstract: An ultra-low-noise one-stage SiGe heterojunction bipolar transistor amplifier was designed for cryogenic temperatures and a frequency range of 10 kHz-100 MHz. A noise temperature T(N) ≈ 1.4 K was measured at an ambient temperature of 4.2 K at frequencies between 100 kHz and 100 MHz for a source resistance of ~50 Ω. The voltage gain of the amplifier was 25 dB at a power consumption of 720 μW. The input voltage noise spectral density of the amplifier is about 35 pV/√Hz. The low noise resistance and power consumption makes the amplifier suitable for readout of resistively shunted DC SQUID magnetometers and amplifiers.

Variable Class Characteristic Amplifier

Abstract: A power amplifier (PA) adjustably operable between two classes of operation. The range of operation lies in a range of operation between a conventional, linear, conjugately matched Class AB characteristic amplifier and a higher efficiency switching Class E characteristic amplifier. A circuit topology having a push-pull configuration (Ql, Q2 ) that allows a Class E characteristic of operation.

System and method for high-frequency amplifier

Abstract: A system and method for operating an amplifier system is provided. The amplifier system includes an input providing a direct coupling configured to receive a high-frequency input signal having a frequency in at least one of a radiofrequency (RF) and microwave range. The amplifier system also includes an amplifier including a dielectric material separating at least two superconducting layers forming an amplifier loop configured to receive the high-frequency input signal and deliver an amplified signal. The amplifier system includes an output providing a direct coupling configured to deliver the amplified signal.

Multi-level boosted class d amplifier

Abstract: Techniques to generate boosted multi-level switched output voltages from a boosted multi-level Class D amplifier. The amplifier may include a multi-level H-bridge, which may include pairs of transistor switches coupled to a first, second, and third supply potential. The second supply potential may be a boosted representation of the first supply potential. The amplifier may receive an input signal, and from the input signal may generate pulse-modulated control signals to control the switching for the transistor switches of the multi-level H-bridge. The amplifier may generate the boosted multi-level switched output voltages from output nodes of the multi-level H-bridge.

Power amplifier with transistor input mismatching

Abstract: A power amplifier includes an input module. The input module includes a transformer and is configured to receive a radio frequency signal and generate output signals. Impedance transformation modules each of which having an output impedance and configured to receive a respective one of the output signals from the transformer. Switch modules each of which comprising a transistor and connected to an output of one of the impedance transformation modules. The transistor has an input impedance and outputs an amplified signal. Each of the output impedances is mismatched relative to a respective one of the input impedances.

A 45-GHz SiGe HBT amplifier at greater than 25 % efficiency and 30 mW output power

Abstract: An efficient power amplifier (PA) is demonstrated in a 0.12-µm silicon germanium (SiGe) BiCMOS process at 45 GHz. The amplifier is a single stage common-emitter amplifier (CE). The voltage handling capability of the amplifier is extended by a low impedance biasing network. The amplifier achieves a peak power-added efficiency (PAE) of 25 % at an output power of 13 dBm in linear operation and 31% in class B mode at an output power of 13.3 dBm. The maximum saturated output power P sat is 14.8 dBm, at which the circuit consumes 77 mW. The chip occupies an area of 0.27 mm2 including pads.

Wideband RF power amplifier for multi-mode multi-band applications

Abstract: A Multi-Mode Multi-Band (MMMB) radio frequency (RF) power amplifier circuit operating at multiple frequency bands. The power amplifier circuit comprises a single wideband power amplifier having high output impedance which is configured to be equal to a load impedance of the load connected to the power amplifier circuit. A bias voltage applied to the wideband power amplifier is changed from a first value to a second value to provide a predetermined output power of the wideband power amplifier to the load with the output impedance of wideband power amplifier being equal to the load impedance. The power amplifier circuit also includes an individual harmonic filter for filtering each frequency band independently.

Hybrid flat gain C-band optical amplifier with Zr-based erbium-doped fiber and semiconductor optical amplifier

Abstract: An efficient gain-flattened C-band optical amplifier is demonstrated using a hybrid configuration with a Zirconia-based Erbium-doped fibre (Zr-EDF) and a semiconductor optical amplifier (SOA). The amplifier utilizes a two-stage structure with a midway isolator to improve flat gain characteristic and reduce noise figure. At input signal power of −30 dBm, a flat gain of 28 dB is obtained from wavelength region of 1530 to 1560 nm with gain variation of less than 4 dB. The noise figure is maintained below 11 dB at the flat-gain region. This amplifier has the potential to be used in the high channel count dense wavelength division multiplexing system due to its simplicity and compact design.

Microwave WPT to a rover using active integrated phased array antennas

Abstract: The high power transmitter active integrated phased array antenna and the rectenna array for the microwave wireless communication and power transmission are demonstrated at 5.8 GHz. The 4 W high power GaAs FET amplifier was developed for the transmitter antenna with the total power of 120 W. The average distance to the rover was 2.5 m. The active integrated phased array antenna with the beam steering function was operated with the 4-bit digital phase shifter by the thin LTCC substrate. In this array, the MSK modulation with the AB-class operation by the high power amplifier was adopted and obtained the BER of 10-6.

Low-Noise Amplifier with Impedance Boosting Circuit

Abstract: A low-noise amplifier (300) is provided which comprises an input circuit (301) configured to operate with a variable bias current and an impedance boosting circuit (314) electrically connected to the input circuit (301). The impedance boosting circuit (314) comprises at least one switch (316) and at least one tail inductor (318) electrically connected with the at least one switch (316). The low-noise amplifier (300) is configured to activate the impedance boosting circuit (314) if the variable bias current is reduced, and the impedance boosting circuit (314) is configured to increase the input impedance of the low-noise amplifier (300) if the impedance boosting circuit (314) is activated.

A 20 W GaN HEMT VHF/UHF Class-D power amplifier

Abstract: A 50 to 550 MHz wideband gallium nitride (GaN) HEMT power amplifier with over 20 W output power and 63% drain efficiency has been successfully developed. The demonstrated wideband power amplifier utilizes two GaN HEMTs and operates in a push-pull voltage mode Class D (VMCD). The design is based on a large signal simulation to optimize the power amplifier's output power and efficiency. To assure a wideband operation, a coaxial line impedance transformer has been used as part of the input matching network; meanwhile, a wideband a 1∶1 ferrite loaded balun and low pass filters are utilized on the amplifier's output side instead of the conventional serial harmonic termination.

Low noise amplifier having both ultra-high linearity and low noise characteristic and radio receiver including the same

Abstract: Disclosed herein is a low noise amplifier having both ultra-high linearity and a low noise characteristic and a radio receiver including the low noise amplifier. The low noise amplifier includes a first main transistor unit, a first auxiliary transistor unit, and an optimum noise and input impedance matching capacitor. The first main transistor unit includes a first NMOS transistor and a first PMOS transistor configured to form a complementary common source amplifier, a feedback-type resistor connected between drains of the first NMOS transistor and the first PMOS transistor and configured to generate biases to the two transistors, and bias resistors connected to bodies of the first PMOS transistor and the first NMOS transistor. The first auxiliary transistor unit includes transistors connected to the two transistors. The optimum noise and input impedance matching capacitor is connected to output terminals of the first main transistor unit and the first auxiliary transistor unit.

High efficiency multiple power mode linear radio frequency power amplifier

Abstract: The embodiments disclosed in the detailed description include a power amplifier having a low power mode amplifier, a medium power mode amplifier, and a high power mode amplifier in communication with a radio frequency (RF) output load. The exemplary embodiments of the power amplifier permit a wireless device to select the most power efficient means to transmit an RF signal based upon the desired output power level.

Wide band high-efficiency power amplifier design

Abstract: This paper presents a hybrid (passive & active) power amplifier concept for a wideband high drain efficiency power amplifier design. The proposed design integrates for the first time a dual-band PA with an active second harmonic injection to achieve high efficiency across a continuous wideband frequency range of two octaves. The design utilizes a resistively loaded class B at the lower frequencies and a class J mode of operation at the upper frequency band. To maintain high efficiency during the transition between the two PA modes an active second harmonic injection at the output of the main transistor is employed through an addition of an auxiliary low power amplifier. To demonstrate the validity of the novel concept a demonstrator is realized around a 10 W GaN transistor with an average efficiency of 63% across 0.6–2.4 GHz at only modest gain compression of 1dB.