Showing papers on "FET amplifier published in 2016"

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

Abstract: In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based OTAs With CMFB Through Supply Rails

Abstract: Multichannel neural amplifiers are commonly implemented with a shared reference whose input impedance is several times lower than that of the corresponding signal inputs. This huge impedance mismatch significantly degrades the total common mode rejection ratio (TCMRR) regardless of the amplifier’s intrinsic CMRR (ICMRR). This study reports a multichannel neural amplifier system that eliminates this impedance mismatch problem by using single-ended CMOS-inverter-based preamplifiers for both the reference and signal inputs. A common-mode feedback (CMFB) loop through the supply rails of the preamplifiers is implemented to enhance their ac input common mode range to $220\;\text{mV}_\text{pp}$ and their ICMRR to more than 90 dB at low frequencies. The ICMRR is maintained above 80 dB up to 1 kHz by minimizing the load drive mismatch between the signal and reference preamplifiers. Implemented in a CMOS 65 nm process, this 16-channel amplifier system operates at 1 V and consumes $118\; \upmu\text{W}$ . It has input referred noise of $4.13\; \upmu\text{V}_\text{rms}$ , leading to a noise efficiency factor (NEF) and a power efficiency factor (PEF) of 3.19 and 10.17, respectively. In vivo recordings of cortical neurons of a macaque were successfully acquired, demonstrating the ability of the amplifier to acquire neural signals in an unshielded environment.

Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology

Abstract: This brief presents the analysis and design of a two-stage stacked power amplifier (PA) with very broadband gain frequency response and power performance in a small chip size. The broadband load impedance match is realized using modified stacked field-effect transistors (FETs) with a resistive feedback by analyzing the matching condition of the source input impedance of the stacked FET. In order to further improve the broadband gain frequency response, the effectiveness of a gain expansion from a stacked driver amplifier is demonstrated to compensate the gain compression of the last-stage amplifier. To verify the design concept, a two-stage three-stacked PA has been implemented in a 0.18- $\mu\mbox{m}$ CMOS technology. The PA achieves a saturated output power of 22–24.3 dBm and a power added efficiency of 13%–20% within a 194% fractional bandwidth from 0.1 to 6.5 GHz. It also demonstrates better than 11-dB input return loss (RL) and better than 5.1-dB output RL. This PA occupies a chip size of 0.64 mm2 including pads.

An over-67-GHz-bandwidth 2 Vppd linear differential amplifier with gain control in 0.25-µm InP DHBT technology

Abstract: In this report, a differential linear amplifier for high-symbol-rate multilevel transmission is presented. We designed and fabricated the amplifier IC by using newly developed in-house 0.25-µm InP DHBT technology, which yields peak ƒt and ƒmax of over 400 GHz. This amplifier consists of lumped variable-gain amplifier and distributed output buffer for achieving large gain control range and ultra-broadband performance. The −3 dB bandwidth and the differential gain are over 67 GHz and 10.7 dB, respectively. Output return loss is better than −10 dB up to 63 GHz. In addition to the ultra-broadband characteristics, nearly 10-dB variable gain range are obtained. The amplifier provides clear output waveform at a symbol rates up to 100 Gbaud with NRZ signal, and up to 56 Gbaud with PAM4 signal respectively.

A SiGe-based broadband 100–180-GHz differential power amplifier with 11 dBm peak output power and >1.3THz GBW

Abstract: A high-gain broadband power amplifier (PA) implemented in a 130-nm SiGe BiCMOS technology is presented. The architecture is based on a class-A four stage fully-differential cas-code amplifier. Each stage is directly matched to the subsequent stage, using a 4-reactance wide-band matching network. On-wafer characterization of the amplifier shows a peak differential gain of 24.8 dB with a 3-dB bandwidth spanning from 100 GHz to around 180 GHz (limited by equipment bandwidth). The amplifier demonstrates a peak differential output power of 11 dBm at 160 GHz and more than 7.5 dBm output power over the entire D-band. The amplifier consumes around 97 mA from a 2.7 V supply. The circuit is the first Si-based power amplifier covering the full D-band. It achieves a record gain-bandwidth product of >1.39THz in D-band, an exceptional GBW/P DC ratio of more than 5 GHz/mW and a state-of-the-art output power at 160 GHz and 170 GHz in Si-based circuits.

In-pixel differential transconductance amplifier for adc and image sensor architecture

Abstract: An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal.

Harmonics suppression circuit for a switch-mode power amplifier

Abstract: Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.

Novel design of highly-efficient concurrent dual-band GaN Doherty power amplifier using direct-matching impedance transformers

Abstract: A novel methodology for designing concurrent dual-band Doherty power amplifier (DPA) is presented in this paper. The required impedance conditions of the carrier amplifier to achieve high-efficiency performance at back-off region are discussed from a new perspective. A novel combine network with direct-matching impedance transformers is then presented to support the load modulation conditions for concurrent dual-band operations. A 1.8–2.6 GHz dual-band Doherty amplifier employing commercial GaN devices is then designed and implemented to validate the proposed method. The fabricated power amplifier (PA) achieves 72% and 60% efficiency for saturation operation at 1.8 and 2.6 GHz, respectively. For the 6 dB back-off region, the measured efficiencies are 63% and 51% in the two designed bands.

A study on positive-feedback configuration of a bipolar SiC high temperature operational amplifier

Abstract: This paper reports on the design and implementation of an integrated operational amplifier in bipolar SiC, and elaborates on its operation in positive-feedback configuration. The opamp is studied i ...

A microwave cryogenic low-noise amplifier based on sige heterostructures

Abstract: A low-noise cryogenic amplifier for the measurement of weak microwave signals at sub-Kelvin temperatures is constructed The amplifier has five stages based on SiGe bipolar heterostructure transistors and has a gain factor of 35 dB in the frequency band from 100 MHz to 4 GHz at an operating temperature of 800 mK The parameters of a superconducting quantum bit measured with this amplifier in the ultralow-power mode are presented as an application example The amplitude–frequency response of the “supercon-ducting qubit–coplanar cavity” structure is demonstrated The ground state of the qubit is characterized in the quasi-dispersive measurement mode

Demonstration of a 0.325-THz CMOS amplifier

Abstract: This paper presents a 0.325-THz single-ended amplifier designed in a 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and utilizes staggered-tuning along with inductive feedback (drain to gate) technique to boost up the gain over a wide frequency band. Having a total power consumption of 28 mW, the amplifier achieves a peak gain of 4.5 dB at 325 GHz. To the best of authors' knowledge, this is the highest operation frequency demonstrated for a silicon amplifier up to date.

60-GHz CMOS Current-Combining PA With Adaptive Back-Off PAE Enhancement

Abstract: This brief describes the design and implementation of a current-combining power amplifier (PA) with a fully adaptive approach to enhance the output power and the back-off power-added efficiency (PAE). The PA consists of a main amplifier and an auxiliary amplifier. Adaptive biasing technique is employed to shut down or provide optimum bias voltage to the auxiliary amplifier according to the input power level. The 50- $\Omega$ input matching is realized with adaptive power distribution. The output load modulation is accomplished by a compact output matching network (MN) using transmission lines and transformers. Based on the same MN, the back-off PAE degradation caused by the low output impedance of the auxiliary path is mitigated. The proposed PA is designed at 60 GHz using 65-nm CMOS and is experimentally characterized. The measurement results reveal 16-dBm OP1dB and 14% peak PAE. Approximately 8% PAE at 6-dB back-off is achieved, addressing improved back-off efficiency.

Impedance transformation circuit for amplifier

Abstract: Aspects of this disclosure relate to an impedance transformation circuit for use in an amplifier, such as a low noise amplifier. The impedance transformation circuit includes a matching circuit including a first inductor. The impedance transformation circuit also includes a second inductor. The first and second inductors are magnetically coupled to each other to provide negative feedback to linearize the amplifier.

Power management in an electronic system through reducing energy usage of a battery and/or controlling an output power of an amplifier thereof

Abstract: A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

Hybrid circuit including a tunnel field-effect transistor

Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

An adaptive slew rate and dead zone ring amplifier

Abstract: This paper presents an adaptive ring amplifier that introduces a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same opera ting frequency. Moreover, it achieves a 40% improvement in the operating frequency for the same linearity and settling requirements. The proposed ring amplifier has been implemented and simulated in a low-cost CMOS 130nm technology while operating from a single 1.2V supply. It has a 98% area reduction compared to the conventional ring amplifier for the same stability conditions.1

eGaN FET based 6.78 MHz Differential-Mode ZVS Class D AirFuel Class 4 Wireless Power Amplifier

Abstract: The ongoing evolution of highly resonant wireless power solutions, enabled by eGaN FETs, continues in this paper where a 33 W capable AirFuel compatible Class 4 power amplifier is presented. As the wireless power levels and charge surface areas increase, so do the design challenges. A 10 W eGaN FET zero voltage switching (ZVS) class D amplifier has been demonstrated as being capable of driving the entire AirFuel Class 2 impedance range without additional circuitry. Unfortunately, given the large increase in impedance range for AirFuel Class 4 systems, this may no longer be possible. This paper delves into the many challenges faced to realize a Class 4 wireless power amplifier solution that include, device thermals, device voltage limits, device selection, impact of timing, and design of support circuitry on the performance of the amplifier and devices. An experimental system is tested and the results show that despite the higher current and power levels, eGaN FETs continue to make inroads into realizing highly resonant loosely coupled wireless power solutions.

Design of a broadband high efficiency GaN power amplifier for GNSS applications

Abstract: This paper presents the design, implementation and experimental results of a broadband high efficiency GaN-HEMT power amplifier. The source-pull and load-pull simulations were employed to determine the optimum input and output impedance of a GaN transistor over 0.9–1.5 GHz in terms of maximum power added efficiency (PAE). A low-pass network based on a closed-form solution was applied for impedance matching and then it was transferred to a band-pass network. Norton Transformation was used to scale up impedances without sacrificing bandwidth or matching. For large signals, the amplifier can achieve a power gain of 9.5–13.5 dB across 0.9–1.5 GHz while the output power is 10–22W. The corresponding power added efficiency (PAE) is 60%–86%. This power amplifier is suitable for satellite communications systems and GNSS applications.

On the modeling of high power FET transistors

Abstract: The paper address some of the problems faced when modeling high power and high power density GaN and GaAs FETs. When operating a high power levels (>1kW) additional effects are observed in GaN devices that are not seen in low power operation (1W). Similar effects start to act on GaAs devices when operated at high power densities. In order to account for these effects, FET models were extended to include temperature, and bias dependence of the access resistances, as well as inflection points in the transconductance, and capacitances. Thus enabling accurate models of the latest generation of enhancement mode, KV range FETs. The recent extensions are evaluated, implemented, and available in major CAD tools like ADS, Cadence, and Microwave office.

Design of multi-octave highly efficient 20 watt harmonically tuned power amplifier

Abstract: In this contribution, a design, implementation, and experimental results of a highly efficient, multi-octave bandwidth power amplifier (PA) using a 25 W packaged GaN-HEMT are presented. Source/load-pull setup is used to extract the optimum source/load impedances across 1.1 – 2.7 GHz. The harmonics impact is considered to improve the power amplifier efficiency. Utilizing the characteristics of FET transistor leads to modify the optimum fundamental load impedances of the low frequency range, which have higher gain compared to high frequency range, and minimize the influence of the higher harmonics. This method results in a measured minimum output power of 43 dBm with a drain efficiency ranged between 65 % to 75 % and a flat gain of 10.5 ±1 dB over the desired band.

Power supply systems and methods for generating power with multiple amplifier paths

Abstract: A power supply system includes a power converter configured to generate a high-frequency power signal and be connected to a load to supply a plasma process or gas laser process with power. The power converter includes at least one amplifier stage having first and second amplifier paths each having an amplifier. The first and second amplifier path are connected to a phase-shifting coupler unit that is configured to couple phase-shifted output signals from the first and second amplifier paths to form the high-frequency power signal. At least one amplifier of the first and second amplifier paths includes a field effect transistor implemented in a semiconductor device with a semiconductor structure having a substantially layered construction, and the semiconductor device includes a channel, a current flowing in the channel substantially in parallel with layers of the semiconductor structure.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-Based Current Amplifier

Abstract: Purpose To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. Methods The resonant detection coil is connected in parallel with the gate of a high electron mobility transistor (HEMT) transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor's source to a negative resistance on its gate. Results High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 μW, 14 dB gain was obtained with excellent noise performance. Conclusion An integrated current amplifier based on a HEMT can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. Magn Reson Med, 2015. Published 2015. This article is a U.S. Government work and is in the public domain in the USA.

Stability analysis and demonstration of an X-band GaN power amplifier MMIC

Abstract: High power amplifier design always requires a compromise between performance and stability. The goal is to design an amplifier that is stable under all operating conditions without sacrificing too much performance by the introduction of stability improvement measures. This paper describes the design of an X-band GaN High Power Amplifier MMIC and the performed stability analysis and measures taken. The amplifier is designed to operate over a wide range of drain bias voltages and input power levels, making the stability analysis particularly important. Using the applied analysis techniques a stable amplifier design has been realized. The measurements show a maximum pulsed output power of 20 W at 30 V drain bias and a maximum PAE of 45% at 18V drain bias. The output power can be adjusted by changing either the drain bias or drive level, while maintaining a good efficiency.

Optimized peaking amplifier of Doherty amplifier using an inductive input second harmonic load

Abstract: An optimized peaking amplifier for proper operation of a Doherty amplifier is investigated. The peaking amplifier operates at a class-C bias and has a lower maximum output power than that of the carrier amplifier. Because of the low output power of the peaking amplifier, the load modulation of the Doherty network cannot be properly carried out. To solve the problem, an inductive second harmonic load is employed at the input. The conduction angle of the input voltage waveform is enlarged due to the out-of-phased second harmonic, restoring the decreased conduction angle and output power. In addition, the peaking amplifier turns on at a higher input power and the first peak efficiency of the Doherty amplifier is enhanced. Based on the concept of the inductive input harmonic load of the peaking amplifier, a Doherty amplifier is implemented with the GaN pHEMT MMIC process at 2.14 GHz and demonstrated the expected good performance.

A 104GHz–117GHz power amplifier with 10.4% PAE in thin digital 65nm Low Power CMOS technology

Abstract: This paper presents a wide band 110GHz power amplifier in thin digital 65nm Low Power (LP) CMOS technology. The amplifier consists of 4 stages of single-ended common source (CS) amplifiers with Shielded Microstrip Line (S-MSL) based inter-stage and input-output matching networks. To address the decoupling issue of single-ended stages, a compact decoupling structure based on distributed inter-digitized MOM capacitor is implemented. The full wave electromagnetic simulations of the decoupling structure show an input impedance of 0.47-j0.12 Ω at 110 GHz. The measured maximum small signal gain of the power amplifier is 17.8 dB at 109 GHz with a 3 dB bandwidth of 13 GHz (104–117 GHz). The OP1dB is 8.25 dBm, while the saturated output power is 9.6 dBm at 112.5 GHz with 10.4% power added efficiency (PAE). The amplifier occupies an area of 340×400µm2 including RF pads.

Power amplifier device and circuits

Abstract: A multi-mode multi-band power amplifier and its circuits are provided. The power amplifier comprises a controller, a wide-band amplifier channel, and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives a single-band or a multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer comprises a first segment shared by RF signals in all bands, second segments respectively specific to RF signals in all bands, and a switching circuit controlled by the controller to separate a RF signal which is subject to power amplification to the second segment in a switchable manner for multiplexed outputs. A power amplifier output power control circuit, a gain switching circuit, and a gain attenuation circuit are also provided.

Phase-Tunable Temperature Amplifier

Abstract: Coherent caloritronics, the thermal counterpart of coherent electronics, has drawn growing attention since the discovery of heat interference in 2012. Thermal interferometers, diodes, transistors and nano-valves have been theoretically proposed and experimentally demonstrated by exploiting the quantum phase difference between two superconductors coupled through a Josephson junction. So far, the quantum-phase modulator has been realized in the form of a superconducting quantum interference device (SQUID) or a superconducting quantum interference proximity transistor (SQUIPT). Thence, an external magnetic field is necessary in order to manipulate the heat transport. Here, we theoretically propose the first on-chip fully thermal caloritronic device: the phase-tunable temperature amplifier. Taking advantage of a recent thermoelectric effect discovered in spin-split superconductors coupled to a spin-polarized system, by a temperature gradient we generate the magnetic flux controlling the transport through a temperature biased SQUIPT. By employing commonly used materials and a geometry compatible with state-of-the-art nano-fabrication techniques, we simulate the behavior of the temperature amplifier and define a number of figures of merit in full analogy with voltage amplifiers. Notably, our architecture ensures infinite input thermal impedance, maximum gain of about 11 and efficiency reaching the 95%. This device concept could represent a breakthrough in coherent caloritronic devices, and paves the way for applications in radiation sensing, thermal logics and quantum information.

Experimental characterization and control of stability margins in microwave amplifiers.

Abstract: Robust design of microwave amplifiers implies the lack of undesired autonomous frequency components for operating conditions that can be very far from nominal. However, microwave amplifiers are prone to exhibit spurious oscillations of different nature and at different frequencies due to the large band gain of microwave transistors and their intrinsic non-linear behavior. To analyze the robustness of a design with respect to spurious oscillations, local stability analyses at simulation level could be performed. However, reliable models and fine circuit descriptions are not always availabe which often makes simulation impractical to analyze the robustness of an aplifier in terms of stability margin.In this context, the goal of this thesis is to develop an experimental technique to characterize critical resonances departing from accurate measurement data that are coherent with the amplifier normal functioning. The method is based on applying pole-zero identification technique to analyze the stability of microwave circuits in samll.signal and large-signal periodic regimes. A systematic methodology ofr microwave circuit stabilization has also been presented, since this can be very useful for the experimental contro of the stability margins.The proposed experimental technique for microwave circuit stability analysis has been applied to several prototypes in hybrid microstrip technology to demostrate its reliability: an L-band FET amplifier in DC regime, a dual mode WiFi-WIMAX amplifier in large-signal regime, and a GaN power amplifier in both regimes.

A 275 GHz amplifier in 0A3μm SiGe

Abstract: This paper presents a 275 GHz amplifier in an advanced 0.13 μm SiGe technology, which has been developed during the European funding project DOTSEVEN, featuring a f T/ f max of 350/550 GHz. Thus the amplifier operates at 1 f max . Utilizing a pseudo-differential common-base topology, it employs an inductive series-series feedback element at the single stage level to increase the maximum available gain while maintaining unconditional stability over the whole measured frequency band. To convert the differential input and output of the amplifier to single-ended ones for on-wafer measurements, a new wideband Marchand balun has also been developed and is presented here. Including balun losses of 5 dB in total, the amplifier has measured 10 dB gain at 275 GHz with a 3 dB bandwidth of 7 GHz. It consumes 69.3 mA from a 1.77 V supply. To the authors best knowledge, this amplifier has the highest operational frequency reported to date in any SiGe technology.