Topic
FET amplifier
About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.
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03 Jun 2007TL;DR: In this article, a Doherty amplifier with gallium nitride (GaN) high-electron-mobility transistors (HEMTs) was used to achieve a drain efficiency of 50% at an output power of 45 dBm.
Abstract: A novel high-efficiency Doherty amplifier is presented. A carrier amplifier and a peak amplifier in the Doherty amplifier are set to asymmetrical drain voltages to extend the power range where a high drain efficiency of the Doherty amplifier is maintained. Matching circuits of the carrier amplifier and the peak amplifier are designed for each drain voltage so that the drain efficiency and signal linearity of the Doherty amplifier at a 9 dB backoff point from its saturated output power (Psat) become higher than those of a conventional Doherty amplifier. These simple steps optimize the power range of the Doherty amplifier for a wideband code-division multiple-access (W-CDMA) signal that has a peak-to-average power ratio (PAR) of 9 dB. A Doherty amplifier containing gallium nitride (GaN) high-electron-mobility transistors (HEMTs) achieves an adjacent channel leakage power ratio (ACLR) of -38 dBc and a drain efficiency of 50% at an output power of 45 dBm. This is the highest drain efficiency of a Doherty amplifier for a W-CDMA signal to the best of the authors' knowledge.
31 citations
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22 May 1997TL;DR: In this paper, a single n-channel insulated gate FET (11) with a single floating gate (12) operates asymmetrically in the sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacia of a parasitical gate-drain capacitor (26).
Abstract: A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).
31 citations
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21 Jun 1982TL;DR: In this article, a fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET, which is driven into conduction by residual charge.
Abstract: A fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET. The bipolar transistor is driven into conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of gate drive. Conduction of the bipolar transistor provides faster discharge therethrough of the FET gate, whereby to facilitate faster FET turn-off without reverse gating current and its attendant auxiliary power supply.
31 citations
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16 Feb 2001
TL;DR: An optical amplifier control system provides real-time control of an optical amplifier in response to an analog signal having a large dynamic range as mentioned in this paper, which uses a non-linear analog-to-digital converter, such as a logarithmic-scale analog to digital converter to achieve low relative quantization error.
Abstract: An optical amplifier control system provides real-time control of an optical amplifier in response to an analog signal having a large dynamic range. The optical amplifier control system uses a non-linear analog-to-digital converter, such as a logarithmic-scale analog-to-digital converter to achieve low relative quantization error. The amplifier control system may also use multiple analog-to-digital converters.
31 citations
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30 Aug 2000TL;DR: An amplifier circuit including at least one first input amplifier, at least first second amplifier cascode-assembled with the first amplifier, and at least reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuits being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit is described in this article.
Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.
31 citations