Topic
FET amplifier
About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.
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27 Aug 2007
TL;DR: An operating load locus is defined based on the load-pull analysis which can be used to predict the non-linear transfer function, efficiency, output power, input drive phase and many other factors associated with the outphasing class-E amplifier.
Abstract: In this paper, we discuss a load-pull analysis technique to charaterize the efficiency performance of class-E amplifier in an outphasing power combining scheme. Class-E amplifier has the potential to deliver high efficiency. Class-E amplifier is not an ideal current or voltage source as is required for the traditional analysis of outphasing structures. It requires a phase modulated input signal and has a non-linear transfer characteristic which is a function of load impedance. Here we define an operating load locus based on the load-pull analysis which can be used to predict the non-linear transfer function, efficiency, output power, input drive phase and many other factors associated with the outphasing class-E amplifier. This scheme could also be used to characterize any amplifier class in an outphasing structure.
29 citations
TL;DR: A single-stage multi-path operational amplifier for fast-settling switched-capacitor circuits is presented that significantly improves the DC gain, unity-gain bandwidth, and slew rate compared to the conventional folded-cascode amplifier.
Abstract: In this paper, a single-stage multi-path operational amplifier for fast-settling switched-capacitor circuits is presented. The proposed amplifier uses all idle devices in the conventional folded-cascode amplifier in the signal path and the positive feedback cross-coupled transistors to enhance both the small-signal and large-signal parameters. It significantly improves the DC gain, unity-gain bandwidth, and slew rate compared to the conventional folded-cascode amplifier with the same power consumption and input parasitic capacitance. Extensive circuit level analysis and simulation results using a 90 nm CMOS technology are provided to evaluate the usefulness of the proposed amplifier.
29 citations
Patent•
23 Dec 2003
TL;DR: In this paper, a resistive level-shifting biasing network is used with a capacitor in parallel to couple FET-based amplifier stages from DC to several GHz in a multi-stage amplifier.
Abstract: A resistive level-shifting biasing network is used with a capacitor in parallel to couple FET-based amplifier stages from DC to several GHz in a multi-stage amplifier. The output of the first amplifier stage is connected to the input of the second amplifier stage without a blocking capacitor or level-shifting diodes, allowing a portion of the drain current for the first amplifier stage to be supplied from the second amplifier stage. In a particular embodiment, a distributed amplifier achieved over 20 dB gain from DC to about 80 GHz using three traveling wave amplifier chips.
29 citations
TL;DR: Describes the design, fabrication, and performance of GaAs monolithic low-noise broad-band amplifiers intended for broadcast receiver antenna amplifier, IF amplifier, and instrumentation applications.
Abstract: Describes the design, fabrication, and performance of GaAs monolithic low-noise broad-band amplifiers intended for broadcast receiver antenna amplifier, IF amplifier, and instrumentation applications. The process technology includes the use of Czochralski-grown semiinsulating substrates, localized implantation of ohmic and FET channel regions, and silicon nitride for passivation and MIM capacitors. The amplifiers employ shunt feedback to obtain input matching and flat broad-band response. One amplifier provides a gain of 24 dB, bandwidth of 930 Mhz, and noise figure of 5.0 dB. A second amplifier provides a gain of 17 dB, bandwidth of 1400 MHz, and noise figure of 5.6 dB. Input and output VSWR's are typically less than 2:1 and the third-order intercept points are 28 and 32 dB, respectively. Improved noise figure and intercept point can be achieved by the use of external RF chokes.
29 citations
15 Mar 2015
TL;DR: In this article, the zero voltage switching (ZVS) voltage mode class D amplifier topology was evaluated using eGaN FETs and compared with MOSFETs.
Abstract: The popularity of highly resonant, loosely coupled, wireless energy transfer systems operating at 6.78 MHz has increased dramatically over the last few years. In this paper we present the zero voltage switching (ZVS) voltage mode class D amplifier topology and evaluate its performance as a suitable A4WP Class-3 compliant amplifier using eGaN FETs and compare the performance with MOSFETs. Experimental verification has revealed that the ZVS class D amplifier can inherently drive a reflected load impedance range from +20j Ω though −30j Ω and 1.7 Ω through 57 Ω while maintaining A4WP Class-3 compliance, which is a significantly wider range than any other topology explored as of this date. The eGaN FET based amplifier was found to have 30 % lower losses and operate as much as 17°C cooler when delivering 16 W into the load than a MOSFET version.
29 citations