FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

Instantaneous floating point amplifier

Abstract: An improved instantaneous floating point amplifier is provided having a plurality of cascaded amplifier stages, wherein the gain of a given stage of the amplifier is the square of the gain of the immediately succeeding stage of the amplifier. The number of amplifier stages which are required to implement the amplifier is minimized, and the control logic which is required to decide if a given stage is needed to amplify the input signal to a level within preselected limits is simplified. The amplifier has an automatic nulling feature which permits nulling of the amplifier without loss of data.

Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors

Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.

Push-pull power amplifier

Abstract: A push-pull power amplifier for amplifying an input signal is described where anti-phase signals are generated from the input signal using a first hybrid junction for driving a pair of transistors and where anti-phase transistor output signals are combined in-phase on an output line by using a second hybrid junction. An independent port may be added to the hybrid junction for isolating and terminating even order harmonics and even order intermodulation products.

Device design for enhanced avalanche SOI CMOS

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Improvement of a Class-C Transistor Power Amplifier by Second-Harmonic Tuning

Abstract: Considerations for the effects of second-harmonic reactive terminations on the performances of a UHF class-C transistor power amplifier are presented. An experimental amplifier circuit design using coupled-TEM-bar transmission lines is described. This circuit can vary the fundamental and the second-harmonic impedance terminations of the amplifier independently. With this amplifier circuit, significant improvement in the performance characteristics of a class-C power amplifier were achieved by presenting proper values of second-harmonic reactive terminations, both at the input and the output of the transistor.