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FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.


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Journal ArticleDOI
TL;DR: In this article, the authors present an amplifier module operating at a frequency of 0.48 THz, which represents almost a 50% increase in solid-state amplifier operating frequency compared to prior state of the art, and is the highest reported amplifier to date.
Abstract: In this letter, we present an amplifier module operating at a frequency of 0.48 THz. This represents almost a 50% increase in solid-state amplifier operating frequency compared to prior state of the art, and is the highest reported amplifier to date. The amplifier demonstrates a peak gain of 11.7 dB measured in a waveguide split-block housing. Sub 50-nm InP HEMT transistors with an estimated f MAX > 1 THz are used to achieve this level of performance. The five stage amplifier is realized in coplanar waveguide, and uses monolithically integrated dipole probes to couple the chip from the WR 2.2 waveguide.

105 citations

Patent
09 Oct 2009
TL;DR: In this paper, an error detector that senses a deviation of the amplitude or phase angle of a load current of a power amplifier driver or of a generator is used to adjust tunable parameters to improve impedance matching.
Abstract: A method for tuning a transmitter in order to improve impedance matching to an antenna or to intermediate radio frequency stages uses an error detector that senses a deviation of the amplitude or phase angle of a load current of a power amplifier driver or of a power amplifier. A controller calculates a correction and dynamically adjusts tunable transmitter parameters, which may include values of components in matching networks or bias voltages in the power amplifier or the power amplifier driver, so as to reduce the deviation and thereby improve the impedance matching. The load current of the power amplifier may alternatively be sensed by measuring the duty cycle of its switching mode power supply. A transmitter having a power amplifier and one or more tunable circuit elements incorporates an error detector that senses the amplitude or phase of a load current and a controller that adjusts one or more tunable parameters to reduce impedance mismatch. An integrated circuit device suitable for use in a transmitter includes a power amplifier driver circuit and a detector circuit capable of sensing a load current, and a controller circuit that can adjust tunable parameters either within or external to the integrated circuit. By eliminating directional couplers and integrating the detectors and power amplifier drivers, the size, complexity, and cost of wireless transceivers can be reduced, while efficiency and power consumption are improved through the dynamic adjustment of operating points and impedance matching.

103 citations

Journal ArticleDOI
12 Dec 2007
TL;DR: This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters that consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source.
Abstract: This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .

103 citations

Proceedings ArticleDOI
02 Dec 2001
TL;DR: In this paper, the authors reported a gate delay of 0.29 ps for an n-channel FET and 0.68 ps for a p-channel FDET at a supply voltage of O(0.8 V).
Abstract: Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15 nm. Gate delays (CV/I) of 0.29 ps for n-channel FET and 0.68 ps for p-channel FET are achieved at a supply voltage of 0.8 V. Energy-delay products are 42 pJ-ps/m for an n-channel FET and 97 pJ-ps/m for a p-channel FET, respectively. To our knowledge; these numbers are the best reported to date.

102 citations

Patent
26 Jan 2007
TL;DR: In this article, a chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier (2) having an input chopper and an output chopper for chopping an output signal produced by the first operational transceiver.
Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier (2) having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter (15) will filter the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

101 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231
20227
20211
20202
20193
20184