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FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.


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Patent
Behrooz Abdi1, Gary Stuhlmiller1
08 Mar 1995
TL;DR: In this article, a differential track and hold amplifier (200) was proposed, which includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductor amplifier (214).
Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

23 citations

Patent
04 Sep 2001
TL;DR: In this paper, a single-ended input differential output amplifier (100) and integrated circuit including an amplifier and an amplifier are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM.
Abstract: A single ended input differential output amplifier (100) and integrated circuit including an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage, VBg, is connected to FET (108) through resistor (112) to FET (110). A coupling capacitor (114) is connected between the input RFIN and FET (110). FET (108) may be connected to gate bias voltage VBg through a second gate bias resistor (122).

23 citations

Journal ArticleDOI
TL;DR: In this paper, an analysis of the sensitivity of InGaAs/InP bipolar heterojunction phototransistors (HJPT's) used in pulse code modulated optical communications systems is presented.
Abstract: An analysis of the sensitivity of InGaAs/InP bipolar heterojunction phototransistors (HJPT's) used in pulse code modulated optical communications systems is presented. The minimum detectable power of an HJPT biased at the optimum level is found to increase linearly with bit rate B while because of the fixed transconductance of the FET amplifier, the minimum detectable power of a p-i-n FET increases as B^{3/2} . It is shown that HJPT's can thus have higher sensitivity than p-i-n FET detectors, particularly at high bit rates, and can have comparable sensitivity to APD-FET detectors.

23 citations

Patent
21 Jun 1982
TL;DR: In this paper, a three terminal bidirectional FET circuit is provided by first and second MOSFETs connected drain to drain in series relation between the main terminals, and by gating circuitry providing requisite gate drive to a corresponding FET regardless of the polarity of its correspondent main terminal.
Abstract: A three terminal bidirectional FET circuit is provided by first and second MOSFETs connected drain to drain in series relation between first and second main terminals, and by gating circuitry providing requisite gate drive to a corresponding FET regardless of the polarity of its correspondent main terminal. A current source is connected to a common point between the FET gates, which common gate point is referenced through a resistor and a pair of diodes to the most negative of the main terminals.

23 citations

Patent
Stephen George Harman1
21 Jun 1982
TL;DR: In this article, an intermediate frequency preamplifier of a microwave radio receiver includes an amplifier circuit having a negative feedback path (16, 22, 7) including a directional coupler (7) constituted by two transformers (71, 72).
Abstract: @ An intermediate frequency preamplifier of a microwave radio receiver includes an amplifier circuit having a negative feedback path (16, 22, 7) including a directional coupler (7) constituted by two transformers (71, 72). One port (D) of the directional coupler (7) is terminated with a complex impedance (8, 20), producing a controlled mis-match, which is adjustable to optimize the input return loss of the amplifier without changing the noise figure of the preamplifier. The amplifier circuit has a low impedance output (2) constituted by a common-collector transistor (6) so that the signal reflected back into the directional coupler (7) by the mis-match does not significantly affect the output of the amplifier.

23 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231
20227
20211
20202
20193
20184