Topic
FET amplifier
About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.
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Patent•
12 Jan 1994TL;DR: In this paper, the authors proposed an integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD).
Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
20 citations
Patent•
25 Sep 1987TL;DR: In this article, a diamond film layer constituting the device's channel was used to avoid phase cancellation between input and output to avoid the phase cancellation in a common gate amplifier. But the diamond channel was not used in this paper.
Abstract: An FET device especially useful in common gate amplifier circuits used as amplifiers of microwave and millimeter wave signals. The device has a diamond film layer constituting the device's channel. Device geometry is selected so that, in a common gate amplifier circuit, device input and output are impedance matched to avoid phase cancellation between input and output. In one embodiment a boron nitride layer is disposed heteroepitaxially with the diamond channel and separating the channel from the gate. In another embodiment plural such devices are yoked together integrally source to drain in such a manner that charge carriers entering the second and subsequent stages do so at maximum velocity without the need to accelerate from zero or low velocity. The resulting device has a higher power handling capacity, upper frequency range, and dynamic range.
20 citations
NEC1
TL;DR: In this article, a C-band high power amplifier with a single-chip GaN-based FET was successfully developed with a 24-mm wide FET, which achieved the highest CW output power achieved from a single chip FET power amplifier at Cband.
Abstract: A C-band high power amplifier was successfully developed with a single-chip GaN-based FET. At 4.0GHz, the fabricated 24-mm wide FET delivers 62 W and 156W under CW and pulsed operating conditions, respectively with a universal test fixture. The internal matching circuit was designed to be set up in a half-size package as compared to that for GaAs-based comparable-power-level amplifiers. The developed GaN-FET amplifier with 24-mm gate periphery delivers a 61W output power with 10.2dB linear gain and 42% power-added efficiency under CW operating conditions. To the best of our knowledge, this is the highest CW output power achieved from a single-chip FET power amplifier at C-band.
20 citations
TL;DR: In this paper, a two-stage Doherty power amplifier (DPA) using the optimized current of the peaking amplifier is presented. But the performance of the two-tier DPA was not analyzed.
Abstract: This paper presents a method of improving efficiency for the two-stage Doherty power amplifier (DPA) using the optimized current of the peaking amplifier. The DPA has a two-stage structure for both the carrier and peaking amplifiers. The first stage of the peaking amplifier has an adjusted bias condition for a near Class-B operation, while the first stage of the carrier amplifier has a higher Class-AB operation. The gain expansion of the first stage due to its lower gate bias helps the second stage of the peaking amplifier to be biased for light Class-C operation and to have steeper turn-ON characteristics, which leads higher peak output power and higher back-off efficiency. The two-stage DPA was designed for the 2.655-GHz band. Using a downlink long-term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, the overall power gain of 25 dB and a peak output power of 54.2 dBm are experimentally obtained. Using an optimized shape of the peaking amplifier's current, a drain efficiency (DE) of 53% and an adjacent channel leakage power ratio of -30 dBc were obtained at an average output power of 47.8 dBm. A DE of 56.8% and an adjacent channel leakage power ratio of -25 dBc were also obtained at an average output power of 49.5 dBm.
20 citations
Patent•
IBM1
TL;DR: An interface circuit for coupling bipolar ECL logic circuit signals to an FET logic array is described in this article. But the interface circuit is not suitable for high level clocking signals, and it cannot handle high level signals.
Abstract: An interface circuit for coupling bipolar ECL logic circuit signals to an FET logic array. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar ECL logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.
20 citations