FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor

Abstract: A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 $\mu$ m CMOS process occupying 0.17 mm $^{2}$ silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 $\mu {\rm V_{\rm rms}}$ . The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Power amplifier for broad band operation at frequencies above one ghz and at decade watt power levels

Abstract: An octave band decade watt power amplifier is disclosed using compact and efficient MMIC fabrication techniques. The power amplifier is a two stage amplifier in which the driver transistor has two cells, and the power transistor has four cells, with each power cell double the size of the driver cells. Both transistors are of an optimized topology facilitating efficient broad band operation at matchable impedance levels. They are interconnected by three four section impedance matching networks of which the input network is coupled to a 50 ohm signal input terminal. The input and the interstage network are both formed on the same substrate as the transistors. The output network is formed on a separate substrate having a high dielectric constant (i.e. 37) which facilitates efficient and compact matching of four power transistor cells to a single output terminal for connection to a load at the conventional (50 ohm) impedance.

Circuit and method of cancelling leakage current in an analog array

Abstract: A field programmable analog array cell (10) uses programmable impedance blocks (12, 18, 22, 24) in the feed-forward and feed-back paths of an amplifier (14) to set the overall function of the array The impedance blocks use switches (34, 38, 42, 46) to program the desired impedance value The switches induce leakage currents into the amplifier inputs which cause drift in the output voltage A compensation circuit (28) providing a compensation current of opposite polarity to the leakage current to the same amplifier input to cancel its effects Alternately, a compensation circuit (30) provides a compensation current having the same polarity as the leakage current to the opposite amplifier input to cancel its effects A p-channel transistor (50) and n-channel transistor (52) are sized to one-half the total diffusion area of like semiconductor devices in the switching circuits

Radio frequency power detecting circuit and method therefor

Abstract: A circuit for detecting the amount of radio frequency power provided by an amplifier. The circuit contains an array of coupled transistors in two power amplifiers, and a log-detector circuit, all resident on a single semiconductor die. The main power amplifier contains the larger array of transistors to amplify the radio frequency signal for feeding to an antenna, and a secondary power amplifier contains a smaller array of transistors to provide a scaled output that is proportional to the amplified radio frequency signal and is used to control the main power amplifier. The log-detector circuit converts the signal from the secondary power amplifier to a full-wave rectified log-linear DC signal that is logarithmically proportional to the controlling signal. The DC signal output from the log-detector circuit is fed to the main power amp to control it.

Balanced dual-detector receiver for optical heterodyne communication at Gbit/s rates

Abstract: A balanced dual-detector receiver which requires low local-oscillator power has been designed and fabricated for optical heterodyne detection at 1·5 ?m wavelength and Gbit/s rates. The receiver consists of two InGaAs PIN photodiodes connected with opposite polarities to a high-impedance GaAs FET amplifier. Frequency response, noise suppression and noise spectrum measurements are reported.