FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy

Abstract: A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

MOS array multiplier cell

Abstract: A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.

A fully-integrated bandpass amplifier for extracellular neural recording

Abstract: This paper describes a fully-integrated bandpass amplifier for neural recording applications. Diode-connected sub-threshold-biased NMOS transistors in the feedback loop of the amplifier realize the high on-chip impedance necessary to eliminate the dc baseline potential of the electrode while amplifying neural field and action potentials. The amplifier has an in-band gain of 38.2dB, a dc gain of 0, an upper cutoff frequency of 24kHz and a low frequency cutoff of 66mHz. It consumes 92/spl mu/W from /spl plusmn/1.5V supplies and has an input-referred noise of 16.6/spl mu/Vrms integrated from 100Hz-10kHz. The amplifier occupies 0.082mm/sup 2/ in 3/spl mu/m features and is being used on a 64-site neural recording probe.

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

Abstract: A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

GaN-Based Device Cascoded with an Integrated FET/Schottky Diode Device

Abstract: A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate.