FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM

Abstract: Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. This paper describes two sensing techniques to overcome this problem: a current sense amplifier (CSA) and a charge transfer sense amplifier (CTSA) and their implementation based on 90 nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier, for the same energy. The other is a charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. The CTSA shows an improvement of 18-22% for read delay for 128 memory cells and consumes 15-18% less energy than the voltage mode sense amplifier. The CTSA results in reduced bit-line swing, which in turn leads to 30% lower bit-line energy than the conventional voltage mode.

Multi-chip doherty amplifier with integrated power detection

Abstract: In accordance with an exemplary embodiment of the present invention, a Doherty amplifier is provided for applications in radio frequency, microwave, and other electronic systems. An exemplary Doherty amplifier comprises a first MMIC having a first power detector, and a second MMIC having a second power detector. The first MMIC and the second MMIC are structurally identical. Furthermore, the first MMIC is configured as a carrier amplifier and the second MMIC is configured as a peaking amplifier. In the exemplary embodiment, an amplifier control bias of the carrier amplifier is a function of the power detected by the first power detector and an amplifier control bias of the peaking amplifier is a function of the power detected by the second power detector. The ability to assemble a Doherty amplifier using a single MMIC product results in a simple and less expensive manufacturing process.

Power amplifier with switched output matching for multi-mode operation

Abstract: Exemplary embodiments are directed to a transmitter with a power amplifier and a switched output matching circuit implementing a plurality of output paths for a plurality of operating modes is described. The power amplifier receives an input RF signal and provides an amplified RF signal. An output matching network performs impedance transformation from low impedance at the power amplifier output to higher impedance at the matching network output. The plurality of output paths are coupled to the output matching network. Each output path provides a different target output impedance for the power amplifier and routes the amplified RF signal from the power amplifier to an antenna when that output path is selected. Each output path may include a matching network coupled in series with a switch. The matching network provides the target output impedance for the power amplifier when the output path is selected. The switch couples or decouples the output path to/from the power amplifier.

Biasing circuit for reducing body effect in a bi-directional field effect transistor

Abstract: A field effect transistor (FET) includes a first source/drain terminal, a body terminal, and a second source/drain terminal. A bi-directional N-channel FET circuit includes a biasing circuit which couples the body terminal of the bi-directional FET to one of its first and second source/drain terminals having a lesser voltage when the first and second source/drain voltages differ by more than a threshold voltage. When the voltages differ by a threshold voltage or less, the body terminal floats at a voltage no higher than a diode drop above the lesser of the two source/drain voltages, and at a voltage no lower than a threshold voltage below the higher of the two source/drain voltages. An analogous bi-directional P-channel FET circuit is also described. Body effect is reduced because the body terminal of the FET is maintained at a voltage at or near the voltage of the effective source terminal at all times, irrespective of which of the two source/drain terminals is the effective source terminal. Consequently, the ON-resistance of the FET is reduced.

Design of Broad-Band Power GaAs FET Amplifiers

Abstract: A model is presented for the drain-gate breakdown phenomenon of GaAs FET's, based on experimental results. this breakdown model is added to a previously published large-signal model and incorporated in a powerful computer-aided design program called LSFET. The program is capable of searching for the optimum power load for an FET and simulating the power performance of multistage amplifiers. The design of power amplifiers is discussed in detail, using the knowledge gained from LSFET. Data is presented from a fabricated monolithic broad-band power amplifier chip showing good agreement between measured results and simulated curves.