FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

A Low-Power Wide-Linear-Range Transconductance Amplifier

Abstract: The linear range of approximately ±75 mV of traditional subthreshold transconductance amplifiers is too small for certain applications—for example, for filters in electronic cochleas, where it is desirable to handle loud sounds without distortion and to have a large dynamic range. We describe a transconductance amplifier designed for low-power (< 1 µW) subthreshold operation with a wide input linear range. We obtain wide linear range by widening the tanh, or decreasing the ratio of transconductance to bias current, by a combination of four techniques. First, the well terminals of the input differential-pair transistors are used as the amplifier inputs. Then, feedback techniques known as source degeneration (a common technique) and gate degeneration (a new technique) provide further improvements. Finally, a novel bump-linearization technique extends the linear range even further. We present signal-flow diagrams for speedy analysis of such circuit techniques. Our transconductance reduction is achieved in a compact 13-transistor circuit without degrading other characteristics such as dc-input operating range. In a standard 2 µm process, we were able to obtain a linear range of ±1.7V. Using our wide-linear-range amplifier and a capacitor, we construct a follower–integrator with an experimental dynamic range of 65 dB. We show that, if the amplifier‘s noise is predominantly thermal, then an increase in its linear range increases the follower–integrator‘s dynamic range. If the amplifier‘s noise is predominantly 1/f, then an increase in its linear range has no effect on the follower–integrator‘s dynamic range. To preserve follower–integrator bandwidth, power consumption increases proportionately with an increase in the amplifier‘s linear range. We also present data for changes in the subthreshold exponential parameter with current level and with gate-to-bulk voltage that should be of interest to all low-power designers. We have described the use of our amplifier in a silicon cochlea [1, 2].

A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications

Abstract: An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier and the linear amplifier are fabricated together in a 150 nm CMOS process, while the second switching amplifier is external. Measurements show a maximum average efficiency of 82% for a 10 MHz LTE signal with a 6 dB PAPR at 29.7 dBm output power and an SFDR of 63 dBc for a single tone of 5 MHz driving an 8 Ω load.

Dual-band, dual-mode power amplifier

Abstract: A power amplifier circuit for a radio transceiver has a linear mode amplifier and a saturated (nonlinear) mode amplifier, a diplex matching circuit coupled to the linear mode amplifier for impedance matching and for separating transmitted signals in a plurality of frequency bands, a low pass matching circuit coupled to the output of the saturated mode amplifier and means for selectably placing the power amplifier circuit in a linear mode for or a saturated mode, corresponding to digital and analog modes of operation of the cellular telephone, respectively in linear or digital mode, the linear amplifier is biased in the on state and the saturated mode amplifier may be biased in the off state. Similarly, in the saturated or analog mode of operation, the saturated mode amplifier is biased in the on state and the linear amplifier may be biased in the off state. The amplifier circuit may include a switch or circuit, coupled to an output of the diplex matching circuit and the output of the low pass matching circuit, for selectably coupling the first diplex matching circuit output or the low pass matching circuit output to an output line when the amplifier circuit is selectably placed in linear mode or saturated mode, respectively.

The transmission-line high-efficiency class-E amplifier

Abstract: High-efficiency switched-mode (heavily saturated) circuits such as the class-E amplifier are well-known in the MHz frequency range. Here, a microwave transmission-line class-E amplifier is presented. Design equations for the output circuit line lengths and impedances are derived, along with approximate equations predicting power and efficiency for the class-E amplifier. Microstrip circuits using the Siemens CLY5 MESFET demonstrate 80% power-added efficiency (PAE) at 0.5 GHz with 0.55 W of output power and 73% PAE at 1.0 GHz with 0.94 W. Experimental results compare favorably to a simplified design-oriented analysis. >

A Simplified "Real Frequency" Technique Applied to Broad-Band Multistage Microwave Amplifiers

Abstract: A computer-aided design (CAD) procedure, which is a new and simplified "real frequency" technique, is introduced for treating the broad-band matching of an arbitrary load to a complex generator. The method can be applied to the design of interstage equalizers for microwave amplifiers. It utilizes the measured data obtained from the generator and the load networks. Neither an a priori choice of an equalizer topology, nor an analytic form of the system transfer function, is assumed. The optimization process of the design procedure is carried out directly in terms of a physically realizable, unit normalized reflection coefficient which describes the equalizer atone. Based on the load-generator matching technique, a sequential procedure to design multistage microwave amplifiers is presented. An example is given for a three-stage, FET amplifier proceeding directly from the measured scattering parameters of the FET devices. The example is in three parts and illustrates the sequential method; that is, first a single-stage, then a two-stage, and finally the three-stage system is computed.