FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

A low power low noise amplifier for a 128 channel detector read-out chip

Abstract: The design of a low-power, low-noise CMOS (complementary metal oxide semiconductor) amplifier is described. The amplifier was designed using the folded cascode configuration and was implemented on a 3- mu m double polysilicon process. The amplifier is part of a 128-channel charge amplifier array chip for use in the readout of radiation detectors with many channels. Aspects of the amplifier design such as bandwidth, pulse response, and noise are discussed, and the effects of individual transistors are shown, thereby relating circuit performance to process parameters. Circuit and radiation test results are included. The results show that a noise level as low as 670 electrons has been achieved with a risetime of 240 ns and a power density of less than 0.45 mW per channel. >

Power amplifier incorporating heterojunction and silicon bipolar transistors

Abstract: A power amplifier including an amplifier stage including a heterojunction bipolar transistor for signal amplification having a base electrode connected to an RF signal input terminal, and a grounded emitter electrode; and a bias circuit including a silicon bipolar transistor having a base electrode connected to a power supply terminal, and a terminal from which a current amplified in response to a base current is output, which terminal is connected to the base electrode of the heterojunction bipolar transistor stage. In this power amplifier, since the voltage required for operating the bias circuit is reduced, a power amplifier capable of operating at a low voltage is realized.

True Filterless Class-D Audio Amplifier

Abstract: The design of a fully integrated, filterless, class-D audio amplifier in standard 0.25- CMOS technology is described: a novel class-D amplifier architecture, where uniform pulsewidth modulation is introduced. The architecture attenuates residual clock signals around the loop allowing very low harmonic distortion, , to be achieved in conjunction with high PSRR, at 217 Hz. When driving 1.2 W into an 8- load, it achieves an SNR of 103 dB (A-weighted) with an efficiency of . The maximum output power at 1% THD is 3.1 W. Figures of merit are defined to establish that the amplifier exceeds the performance of alternative designs. The amplifier occupied a chip area 1.44 and was packaged as a WLCSP.

Low power consumption adaptive power amplifier related application

Abstract: A power amplification circuit (10) includes a scalable power amplifier (20) to produce an RF output signal (50) at an output of the power amplification circuit (10), and a variable impedance circuit (30) coupled to the output of the power amplification circuit (10). The scalable power amplifier (20) includes a plurality of selectively activated amplifier elements (22), (24), (26) to produce the RF output signal (50) in accordance with a desired RF output signal power level. The power amplification circuit (10) selectively activates individual amplifier elements by, for example reducing power or increasing power to at least one amplifier element. The variable impedance circuit (30) varies an impedance of the variable impedance circuit (30) to dynamically load the output of the scalable power amplifier(20).