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FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.


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Patent
21 Jun 1982
Abstract: A three terminal bidirectional FET circuit is provided by first and second MOSFETs connected source to source in series relation between first and second main terminals, and by gating circuitry including current source means connected to a gate terminal for driving the FETs into conduction. A resistor is connected between a point common to the FET sources and a point common to the FET gates and the current source, such that the gate to source voltage for each FET is the same regardless of the relative polarity of the main terminals.

40 citations

Patent
19 Jan 2005
TL;DR: A power amplifier for amplifying radio frequency signals includes a radio frequency power amplifier including one or more semiconductor transistors, adapted to receive an input radio frequency signal and power control signals, and to output an amplified audio signal.
Abstract: A power amplifier module for amplifying radio frequency signals includes a radio frequency power amplifier including one or more semiconductor transistors, adapted to receive an input radio frequency signal and power control signals, and to output an amplified radio frequency signal. The power amplifier module is integrated with input and output impedance matching networks and a power sensor that is adapted to receive the amplified radio frequency signal and to output a signal indicating the power output level of the power amplifier module. The power amplifier module also includes control logic in accordance to at least one of the qualities and the power level of the amplified radio frequency signal.

40 citations

Patent
06 May 1993
TL;DR: In this paper, the authors proposed a differential amplifier with a pair of like-polarity differentially coupled FETs (Q1 and Q2, Q3 and Q4) that divide a tail current (IN, Ip) into two main currents (I1 and 12, 13 and 14) and a square root circuit (24) controls the tail currents in such a way that the sum of their square roots is largely constant.
Abstract: A differential amplifier contains a pair of differential portions (10 and 12) that together provide representative signal amplification across the full amplifier power-supply voltage range. Each differential portion normally contains a pair of like-polarity differentially coupled FETs (Q1 and Q2, Q3 and Q4) that divide a tail current (IN, Ip) into a pair of main currents (I1 and 12, 13 and 14). The two FET pairs are complementary. A square-root circuit (24) controls the tail currents in such a way that the sum of their square roots is largely constant. Consequently, the amplifier transconductance is largely constant.

39 citations

Proceedings ArticleDOI
20 May 2001
TL;DR: In this paper, a nonlinear cancellation technique was developed specifically for MOS class AB power amplifiers, which utilizes a PMOS transistor at the amplifier input to cancel the variation of the input capacitance.
Abstract: A nonlinear cancellation technique is developed specifically for MOS class AB power amplifiers. This technique utilizes a PMOS transistor at the amplifier input to cancel the variation of the input capacitance, thus improving the overall amplifier linearity. A monolithic CMOS RF power amplifier with this technique is designed and fabricated in a standard 0.6 /spl mu/m CMOS technology. The prototype single-stage amplifier has a measured drain efficiency of 40% and a power gain of 7 dB at 1.9 GHz. Linearity measurements show that the new amplifier has over 10 dB of IM/sub 3/ improvement and 6 dB of ACPR improvement compared with the traditional NMOS class AB power amplifier.

39 citations

Patent
03 Sep 1991
TL;DR: In this paper, an amplifier with a high-current NMOS transistor is incorporated with an integrated circuit, where one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected.
Abstract: An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected. The output (collector) of the differential amplifier is connected to the gate of the NMOS driver transistor so that the load current through the driver transistor is held regulated to a value proportional to the input or reference voltage that is applied to the other input of the differential amplifier. The peak pulse voltage of each charge pump is greater than the DC supply voltage from which the driver transistor and the two charge pumps are energized so that the dynamic range of both the input control voltage and the amplifier output to the gate of the NMOS driver transistor is much greater than the DC supply voltage to the integrated circuit.

39 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20231
20227
20211
20202
20193
20184