FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

The dual-fed distributed amplifier

Abstract: A conventional microwave distributed amplifier consists essentially of a gate artificial transmission line and a drain artificial transmission line which have common active components in the form of MESFETs that provide the gate-and-drain-line shunt capacitances. Such amplifiers have an input port to the gate line and an output port from the drain line. The unused gate and drain ports are terminated in the appropriate characteristic impedances. A method is presented or a dual-fed distributed amplifier, using a small number of MESFETs, in which the gain is significantly increased and the noise figure significantly reduced by feeding the signal power into both gate-line ports. Provided the amplifier operates under small-signal (linear) conditions, superposition will apply to its operation, and the output due to two forward gain signals will add to produce the total output power. This arrangement increases available gain from the amplifier in comparison with its conventional mode of operation and a concommitant reduction in noise figure. Examples verifying the design are discussed. >

Power amplifier using upstream signal information

Abstract: A power amplifier system uses upstream signal information of a signal to be amplified by an amplifier to control the operation of the amplifier, thereby enabling the amplifier to operate more efficiently overall. The power amplifier system can reconfigure the amplifier based on upstream signal information, such as the measured peak power, the measured average power, the number of users, the type of carriers (CDMA, TDMA, FDMA), the number of carriers and/or the average power per carrier. For example, based on upstream signal information for the signal to be amplified, processing circuitry can reconfigure the power amplifier architecture to adjust the peak power handling capability of the amplifier. By reducing the peak power handling capability of the amplifier, the long-term efficiency of the amplifier can be improved. The power amplifier system can adjust at least one operating characteristic of the amplifier while maintaining the configuration of the amplifier, for example by adjusting the bias voltage(s) to the amplifier based on upstream signal configuration information.

Time-shared instantaneous gain-ranging amplifier

Abstract: One-hundred low-frequency analog signal channels having a very large dynamic range, may be amplified to at least half of full scale a 14 bit analog to digital converter without distortion by an amplifier system that includes an instantaneous gain-ranger, a preamplifier for each channel, a filter system for each channel, a premultiplexer gain-ranging amplifier for each channel, and a multiplexer. The instantaneous gain-ranger consists of a series of binary amplifier stages, threshold detecting circuitry and logic circuitry. The output is taken from the first unsaturated amplifier. The preamplified and premultiplexer gain-ranging amplifier are connected into the system ahead of the multiplexer and provide a sufficient signal-to-noise ratio to mask the noise introduced into the system by the multiplexer. The output of the system is typically digitized.

Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology

Abstract: This brief presents the analysis and design of a two-stage stacked power amplifier (PA) with very broadband gain frequency response and power performance in a small chip size. The broadband load impedance match is realized using modified stacked field-effect transistors (FETs) with a resistive feedback by analyzing the matching condition of the source input impedance of the stacked FET. In order to further improve the broadband gain frequency response, the effectiveness of a gain expansion from a stacked driver amplifier is demonstrated to compensate the gain compression of the last-stage amplifier. To verify the design concept, a two-stage three-stacked PA has been implemented in a 0.18- $\mu\mbox{m}$ CMOS technology. The PA achieves a saturated output power of 22–24.3 dBm and a power added efficiency of 13%–20% within a 194% fractional bandwidth from 0.1 to 6.5 GHz. It also demonstrates better than 11-dB input return loss (RL) and better than 5.1-dB output RL. This PA occupies a chip size of 0.64 mm2 including pads.

Magnetoresistive head amplifier

Abstract: An amplifier for biasing and amplifying the signals produced by a magnetoresistive element is provided. The input stage of this circuit includes two transistors in a differential common base configuration having a low input impedance. Since the two transistors are coupled to separate identical current sources, balance between the currents through the two transistors is maintained. The currents are balanced without the use of a feedback loop. Additional input stages may be added to allow signals from additional magnetoresistive elements to be selected and amplified. By using a common mode switching configuration, switching transients are greatly reduced.