FET amplifier

About: FET amplifier is a research topic. Over the lifetime, 7048 publications have been published within this topic receiving 77549 citations.

Class E Power Amplifier Design and Optimization for the Capacitive Coupled Wireless Power Transfer System in Biomedical Implants

Abstract: The capacitive coupled wireless power transfer (CCWPT) operating at megahertz (MHz) frequency is broadly considered as the promising solution for low power biomedical implants. The class E power amplifier is attractive in MHz range wireless power transfer (WPT) applications due to zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) properties. The existing design of class E amplifier is investigated only for inductive resonant coupled (IRC) WPT systems; the modelling and optimization of the class E amplifier for CCWPT systems are not deliberated with load variation. Meanwhile, the variations in the coupling distance and load are common in real time applications, which could reduce the power amplifier (PA) efficiency. The purpose of this paper is to model and optimize the class E amplifier for CCWPT systems used in MHz range applications. The analytical model of PA parameters and efficiency are derived to determine the optimal operating conditions. Also, an inductive-capacitive-inductive (LCL) impedance matching network is designed for the robust operation of the PA, which improves the efficiency and maintains required impedance compression. The maximum efficiency of the proposed design reached up to 96.34% at 13.56 MHz and the experimental results are closely matched with the simulation.

Sense amplifier circuit for semiconductor memory

Abstract: A sense amplifier circuit comprises a first amplifier circuit for detecting the data from a memory cell and generating an output signal in accordance with the detected data, a first load MOS transistor of one conductivity type connected between an output terminal of the first amplifier circuit and a power source terminal, a second amplifier circuit for detecting the data from a dummy cell and generating an output signal in accordance with the detected data, a second load MOS transistor of one conductivity type and a third load MOS transistor, which are connected in parallel between an output terminal of the second amplifier circuit and the power source terminal, and a comparator for comparing the output signals from the first and second amplifier circuits and generating an output signal in accordance with the result of the comparison. The third load MOS transistor is a MOS transistor of an opposite conductivity type whose back gate is connected to a reference potential terminal.

Charge injector transistor memory

Abstract: Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required.

Systems and methods for on-chip impedance termination

Abstract: Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

Multi-stage high-performance amplifier

Abstract: A two-stage switched-capacitor CMOS Miller-compensated amplifier uses only n-channel transistors in its signal path to reduce the deleterious effects of parasitic capacitances in the signal path while still obtaining a high transconductance in both stages. A transistor inserted in series with the Miller capacitor between the output and input of the second stage of the amplifier introduces a feedforward zero in the left half of the S-plane of the circuit. By appropriately sizing the aspect ratio and properly biasing this transistor, the second pole of the amplifier is canceled with the introduced zero. Dummy transistors having their sources and drains connected (to serve as capacitors) are cross-connected between opposite polarity inputs and outputs of a differential pair of input transistors in the first stage to effectively cancel the gate-to-drain Miller-multiplied capacitance of the input transistors. A common-mode control current is generated based upon a voltage at a common-source node of a differential pair of input transistors in the second stage. This current is fed back to the first stage to control the common-mode of the first stage.