Showing papers on "Field effect published in 1970"

Field effect semiconductor device having a protective diode

Abstract: A semiconductor device comprising a semiconductor element having an insulated gate electrode and a protective diode region provided in the neighborhood of the semiconductor element to protect the gate electrode from a dielectric breakdown; the diode is formed by a low resistivity semiconductor material to reduce its internal resistance, thereby accelerating the action of the protective diode so that the clamp action of the diode occurs earlier than the dielectric breakdown of the gate electrode.

Complementary insulated gate field effect devices

Abstract: A complementary pair of insulated gate field effect transistors is fabricated in a monocrystalline silicon wafer. The method features the use of doped-oxide diffusion sources, self-aligned, passivated-gate electrodes, and the concurrent diffusion of the source and the drain regions for both the n-channel device and the p-channel device in a single step.

The effect of an applied electric field on the oxidation of aluminum in the temperature range 50–400°C

Abstract: This paper describes some oxidation studies of evaporated aluminum films. Resistance marker measurements were carried out between 230 and 400° C and it was concluded that the oxide grows by metal transport. From the sign of its Seebeck coefficient, the oxide was deduced to ben-type. The effect of applying an electric field across the growing oxide layer on aluminum was also investigated. A porous platinum layer evaporated onto the oxide surface was used as one electrode, the underlying metal being the other electrode. At all temperatures between 50 and 400° C the same field effect was observed. When the oxygen-oxide interface was biased negative with respect to the aluminum, an enhancement of the oxidation rate was achieved. These results have been interpreted in terms of the Mott-Cabrera theory.

Predicted Effects of Neutron Irradiation on GaAs Junction Field Effect Transistors

Abstract: The fast-neutron-induced degradation of the properties of n-channel GaAs junction field effect transistors (JFET) is estimated and the results are compared with the effects produced in n-and p-channel silicon field effect transistors. The estimated degradation of the maximum transconductance, maximum drain current, pinch-off voltage, and cutoff frequency is based on electrical measurement data taken for fast-neutron-irradiated bulk n-type GaAs samples. It is concluded that n-channel GaAs JFET's should be at least as resistant to fast neutrons as either n-or p-channel Si JFET's.

Self-aligned gate field effect transistor with schottky barrier drain and source

Abstract: A LOW PARASITIC CAPACITANCE FIELD EFFECT TRANSISTOR IS FABRICATED BY THE UTILIZATION OF A SELF-ALIGNING GATE TECHNIQUE. A METAL GATE IS FORMED AND THEN, EMPLOYING THE GATE AS A MASK, LOW TEMPERATURE SCHOTTKY BARRIER SOURCE AND DRAIN JUNCTIONS ARE FORMED. THE TECHNIQUE IS PARTICULARLY USEFUL IN THE FABRICATION OF THE FIELD EFFECT TRNASISTOR AS AN ELEMENT OF A LARGE INTEGRATED CIRCUIT WHERE MANY SUCH ALIGNMENTS MUST BE MADE SIMULTANTEOUSLY. D R A W I N G

Ferroelectric field effect studies at low temperatures

Abstract: The ferroelectric field effect has been studied experimentally at low temperatures (300°K > T > 78°K) using n type tin oxide films deposited on polished ferroelectric ceramic (PZT) substrates. It is shown that the film, in its enhanced state, possesses the characteristics of a degenerate semiconductor with the Fermi level 0.60 eV above the conduction band edge. In the depleted state (high resistance) the Fermi level can be as much as 0.28 eV below the conduction band edge. There is evidence of a trapping state that degrades the field effect transition at temperatures below ∼183°K and at 78°K there is only a very small field effect transition even though the substrate switches more polarization charge than at room temperature. The depleted state instability is shown to be due to a thermally activated process with the high resistance being relatively stable with time for temperatures below 253°K.

Processes using a masking layer for producing field effect devices having oxide isolation

Abstract: PART OF THE NITRIDE LAYER IS THEN USED O MASK THE OXIDE FILM DEFINING THE GATE REGION OF THE FEILD EFFECT DEVICE. CONDUCTIVITY REGIONS ARE FORMED IN THE ISLAND BY DIFFUSION AS NITRIDE LAYERS MASK THE CONTACT REGIONS OF THE FIELD EFFECT DEVICES. CONTACTS ARE FORMED ON THE CONTACT REGIONS. OXIDE FILMS AND A NITRIDE LAYER ARE SELECTIVELY FORMED OVER THE SURFACE OF A SEMICONDUCTOR WAFER TO DEFINE AREAS OF THE WAFER IN WHICH FIELD EFFECT DEVISES ARE TO BE FORMED. THE NITRILE LAYER MASKS THE INNER OXIDE FILM AS AN OXIDE LAYER IS FORMED AROUND THE MASKED REGIONS TO FORM LATERALLY ISOLATED SEMICONDUCTOR ISLANDS IN WHICH THE FIELD EFFECT DEVICES ARE TO BE FORMED.

Temperature dependence of the power output of the spontaneous emission from GaAs laser diodes

Abstract: Modulation of photoluminescence in p–type GaAs by a field effect indicated that the radiative recombination occurred through recombination centres. This suggested that the recombination rate in the depletion region of a luminescent p–n junction would be governed by Shockley—Read statistics. The resulting model showed that, with suitable diode parameters, an increase in temperature would produce an increase in the radiative efficiency of the diode. Such an effect was observed experimentally with vapour-grown GaAs p–n junctions, the p–type sides of which were heavily compensated.

Measurements of the Thermal‐Emission Rates of Electrons and Holes at the Gold Centers in Silicon Using the Small‐Signal‐Pulsed Field Effect

Abstract: The small‐signal‐pulsed field effect in the surface‐space‐charge region of a metal‐oxide‐semiconductor field‐effect transistor structure is developed to investigate the properties of gold impurity in the surface region of silicon. Thermal‐emission rates of electrons and holes and their thermal‐activation energies at both the gold‐donor and ‐acceptor states are obtained. At 300°K the low‐field thermal‐emission rates are ep0t+en1t=680/sec at the gold‐acceptor center and ep−1t=1.2×107/sec at the gold‐donor center. Thermal‐activation energy of these emission rates was observed in the range of 216°–370°K for the acceptor center giving EC‐EAu‐=0.54 eV and in the range of 130°–235°K for the donor center giving EAu+‐EV=0.34 eV. The field dependences of the thermal‐emission rate and the spatial distribution of gold concentration in the surface‐space‐charge region of up to 1‐μ wide are observed, indicating a pileup of gold at the interface in phosphorus‐diffused n‐channel devices.

Insulated gate type field effect semiconductor device having narrow channel and method of fabricating same

Abstract: A method for fabricating an integrated gate field effect transistor is disclosed wherein an induced conduction region is formed between the source and drain regions by the application of a suitable potential between the gate electrode and substrate. The surface of the device is irradiated by a high-energy beam, thereby to form a narrow channel in the conduction region which defines the gate channel of the field effect transistor.

Insulated gate field effect transistor adapted for microwave applications

Abstract: Solid state field effect switch devices useful in microwave applications. Devices disclosed embody resistive noninsulative layer material insulated from a supporting semiconductor body. Electrodes connected to the layer material and the body are arranged so that signals applied to one electrode can, by field effect action, alter the electrical conductivity of a path within the device which extends between two other electrodes.

Method of making an insulated gate field effect device

Abstract: An insulated gate field effect device is made by a vapor etch and epitaxial refill technique The vapor etch into a first-type conductivity silicon substrate results in an undercutting between windows such that a cavity is developed completely beneath the insulator separating the window regions The cavity is then refilled epitaxially with silicon of a second conductivity type; a shallow layer of heavily doped silicon of said first-type conductivity epitaxially regrown in the window area; the gate insulator oxide thinned by etching; and gate, source, and drain contacts made

Secondary emission field effect charge storage system

Abstract: A secondary emission field effect charge storage system utilizing a combined NPN and P-channel field effect transistor device. The device includes a body of P-type semi-conductor material and a pair of bodies of N-type semi-conductor material respectively forming PN junctions with opposite sides of the Ptype body in a first dimension thereby forming the NPN transistor, the P and N-type bodies forming the P-channel field effect transistor in a second dimension generally perpendicular to the first dimension. One of the N-type bodies has an outer surface having secondary emissive properties, and a collector electrode is provided for collecting secondary electrons emitted from that surface in response to electron bombardment thereof, with the surface thus having a positive charge stored thereon. A switching system is provided for respectively selectively making first, second and third electrical connections of the other of the pair of N-type bodies and the opposite ends of the P-channel transistor to predetermined potentials. The potentials are applied in the first connection to bias both the NPN transistor and the P-transistor to cut-off thereby to permit charge storage on the surface of the one N-type body. The potentials are applied in the second connection to bias the NPN transistor to cut-off and the P-channel transistor to below cut-off thereby to permit current flow in the P-channel, as modulated by the charge on the surface of the one N-type body to provide a read-out signal. The potentials are applied in the third connection to bias the NPN transistor into conduction and to bias the P-channel transistor to cut-off thereby to neutralize or erase the charge on the surface of the one N-type body.

Field effect semiconductor devices

Abstract: A semiconductor device in which, for example, an insulated gate type field effect transistor is formed in a major surface of an N-type silicon substrate having an edge that is formed by mechanical separation; a P-type region is formed in a portion of the edge area of the substrate or in the entire edge area of the substrate, and a metal electrode for grounding is connected to the P-type region.

Numerical method of investigation for m.o.s.t. structures

Abstract: A numerical method of investigation for m.o.s. structures, which includes the complete system of equations governing the device, is presented with some results for a particular m.o.s. transistor.