Showing papers on "Field effect published in 1977"

Process for making field effect and bipolar transistors on the same semiconductor chip

Abstract: A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.

Random access junction field-effect floating gate transistor memory

Abstract: JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.

Field effect transistor with a short channel length

Abstract: of the Disclosure A field effect transistor with a MIS gate arrangement having a source and drain formed in a semiconductor body and including an electrically con-ductive region additionally provided which lies beneath the source zone and which has a conductivity opposite to and/or electrical conductivity which is higher than the semiconductor body which surrounds the zone and in which in the controllable field effect gate the electrically conductive zone is spaced a distance from the gate and the boundary surface and wherein the gate insulation layer projects laterally a space relative to the source zone which is approximately 1 to 10 times the thickness of the gate insulation layer and the distance from the gate arrangement to the boundary surface is 1 to 5 times the thickness.

Method for forming self-aligned field effect device by ion implantation and outdiffusion

Abstract: A method is provided for making a field effect transistor which comprises forming a layer of an ion beam masking material on the surface of a semiconductor body of one-type conductivity having at least two adjacent apertures with at least a portion of the masking layer between these apertures and in contact with the semiconductor body surface being an electrically insulative material. Then, a beam of ions of opposite-type conductivity is directed at the mask body at an energy and dosage sufficient to form two buried regions of opposite-type conductivity fully enclosed within said one-type body respectively beneath these two apertures. Finally, sufficient heat is applied so that the two buried regions diffuse upward until they extend respectively to the surface of the semiconductor body beneath the two apertures; the masking material must have a melting point above the temperature of the diffusion step.

Liquid crystal cell

Abstract: A nematic liquid crystal cell operating in a field effect scattering mode employs a surfactant to provide homogeneous random alignment of the nematic director. Field effect scattering mode operation improves over dynamic scattering mode operation by using an electric field to switch between homeotropic and homogeneous random alignment.

Push-pull pulse amplifier having improved turn-on and turn-off times

Abstract: A pulse amplifier formed of first and second field effect transistors, each exhibiting an inherent input capacitance at its gate electrode, the field effect transistors being connected in push-pull relation whereby their drain or source electrodes are connected to a common output terminal. First and second resistive circuits are connected in a pulse supply circuit to supply pulse signals to the respective gate electrodes of the field effect transistors. Each of the resistive circuits exhibits a higher resistance when a pulse is supplied therethrough to turn the respective field effect transistor ON and a lower resistance when the pulse is terminated to turn the respective field effect transistor OFF. The higher resistance of the resistive circuit cooperates with the inherent input capacitance of the respective field effect transistor to provide a higher discharge time constant to turn that field effect transistor ON and the lower resistance cooperates with the inherent input capacitance of the field effect transistor to provide a lower charge time constant to turn that field effect transistor OFF, whereby the field effect transistors are not ON concurrently. In a preferred embodiment, the field effect transistors are complementary field effect transistors so that a positive-going pulse turns one of those field effect transistors OFF while turning the other ON, and a negative-going pulse turns the one field effect transistor ON while turning the other OFF.

Memory type insulating gate field effect semiconductor device

Abstract: In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exist on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the read-out voltage of the semiconductor device can be reduced. The circuit design is simplified.

Electron beam forming device

Abstract: The electron beam forming device uses a field effect electron emitter with a control electrode disposed on the surface thereof for field effect release of electrons. The control electrode can be shaped to produce a selective or segmented field for developing a particular current path. However, the shape of the beam is determined by the shape of the conductor of the backing plate which is external to tube housing instead of the internal control electrode. Thus multiple beams can be obtained from one emitting array and the final configuration of the device can be changed after the device is built.

The field effect in amorphous chalcogenides: An investigation of localized states and electronic transport

Abstract: The temperature dependence of the field effect response permits an unambiguous determination of the identity of those states responsible for electrostatic screening in the amorphous chalcogenides. We observe (1) in As2Te3, field effect screening by localized states at the Fermi level at low temperatures (∼ 1019 cm−3 eV−1) and by mobile charge carriers (∼ 1018 cm−3 at 300 K) at high temperatures, and a transition from p-type to two-carrier (primarily n-type) conductivity as the temperature is raised above ∼320 K; (2) in As2SeTe2, screening by mobile charge carriers (∼ 1018 cm−3 at 300 K) with strongly type conductivity; (3) in As2Se2Te, screening by localized states at the Fermi level (∼ 1019 cm−3 eV−1) with strongly p-type conductivity; and (4) in Sb2Te3, a very high density of localized states at the Fermi level (∼ 2 × 1020 cm−3 eV−1) with both electron and hole contributions to the conductivity. Correlation with thermoelectric power results suggests that the p-type conductivity in As2Te3 is due to near-equal contributions from two processes: hopping in localized states plus extended state conduction. Aging and annealing behavior is described with the aid of a “chaotic potential model” that appears to be able to account for large changes in mobile carrier density that leave the conductivity unaltered.

Manufacture of field effect semiconductor device

Abstract: PURPOSE: To manufacture a high-dielectric-strength FET by improving the impurity density of a source and that of a drain by means of an ion injection method, and by preventing the crystal of the gate region from deteriorating. COPYRIGHT: (C)1979,JPO&Japio

Method of fabricating an insulated gate field effect device

Abstract: This invention provides a method of making an improved gate structure in which the gate electrode is self-aligned with respect to the field isolation oxide regions. Gate constituting layers are formed on a substrate prior to formation of the field isolation oxide regions. An oxidation barrier layer is provided on such layers, also covering the other regions which should be formed into the source and drain regions, etc. By etching off the oxidation barrier layer above the field isolation regions, the boundary edges of the gate on the field isolation regions are formed. Then oxidation is performed using the oxidation barrier as a masking pattern to form the field isolation oxide regions. The field isolation oxide regions and the gate thus formed completely coincide with each other at their boundary edges.

On the field effect of the electrical conductance of discontinuous thin metal films

Abstract: In the activated tunneling model of electrical conductance of discontinuous thin metal films, non‐Ohmic conductance has thus far been explained by a field‐dependent activation energy at a high electric field. We point out that this interpretation is not appropriate. Alternatively, the field effect should be ascribed to the non‐Ohmicity of the tunneling current density at a high electric field. Results of the computation are presented.

Field effect type polisilicon resistance element

Abstract: PURPOSE:To use the channel part of the i layer of the poly-Si sandwiched by source and drain as a high resistance by applying a voltage to the substrate side which becomes a gete and modulating its conductivity.

Depletion/enhancement mode FET logic circuit

Abstract: Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages. A number of these open drain logic outputs may be connected together to form DOT logic configurations and the potential swing at these open drain outputs, being a function of the threshold voltage of the subsequent stage input device, is substantially less than the potential difference between the fixed positive and ground supply potentials.

Junction type field effect semiconductor device and its production

Abstract: PURPOSE:To improve the scale of integration of J-FETs and reduce the variation in impurity concentration, by forming a gate region by impurity diffusion in deep grooves formed in an Si substrate through the use of anisotropic etching.

Process for production of semiconductor integrated circuit

Abstract: PURPOSE:To adopt an isolation method involving etching of the recessed portions of Si, and a method of forming two steps of epitaxial grown Si layers, thereby composing an IC consisting of high dielectric strength vertical type field effect and ordinary transistors on one semiconductor substrate.

Field effect type semiconductor device

Abstract: PURPOSE:To suppress the parasitic effect of short channel type transistor operation due to the immersion of depletion layer to conductive domain and to obtain FET with high voltage and high reliability, by providing the conductive type domain with high density governing electric operational performance to the concave portion apart from the inverse conductive type domain.

Process for production of field effect transistor

Abstract: PURPOSE:A process for production of an N-channel depression type field effect transisor (E-DMOS) which does not require ion implantation process by changing surface state density.

Insulating gate type field effect semiconductor device

Abstract: PURPOSE:To improve the operational speed and electric performance, by introducing uniconductive type impurity which is self-aligned only to the channel domain beneath the insulating gate, in MIS transistor in which the insualting gate and inverse conduction type domain are formed on the surface of uniconduction type semiconductor.

Silicon gated* field effect semiconductor device

Abstract: PURPOSE:To improve quality of Si gated, field effect semiconductor by forming polycrystalline Si film on the oxide film for gate under the condition that the former does not extend over the latter.

Complementary type insulated gate field effect semiconductor device

Abstract: PURPOSE:A C-MOSFET wherein an N or P type layer of nearly uniform impurity concentration distribution is provided over a P type or N type semiconductor substrate whereby the base length of parasitically produced transistors are made longer and their amplification factor is reduced.

Display device by electric field light emitting and receiving elements

Abstract: PURPOSE:A display device in which the number of lead wires and switches from the display device is reduced a number of display elements comprising field effect light emission elements are successivley and accumulately lit up.