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Showing papers on "Field effect published in 2001"


Patent
20 Nov 2001
TL;DR: In this paper, a method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility.
Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

242 citations


Journal ArticleDOI
TL;DR: In this paper, the authors used scanning force microscopy (SFM) to perform nanoscale studies of the switching behavior of Pb(Zr, Ti)O3 thin films via the direct observation of their domain structures.
Abstract: Scanning force microscopy (SFM) has been used to perform nanoscale studies of the switching behavior of Pb(Zr, Ti)O3 thin films via the direct observation of their domain structures. The study revealed a significant asymmetry of a switching pattern which is a function of the voltage polarity and original domain structure of individual grains. The phenomenon of asymmetric switching is attributed (1) to the presence of an internal built-in electric field at the bottom interface and (2) to the mechanical stress exerted by the SFM tip. The former effect results in incomplete 180° switching, while the latter effect leads to a 90° rotation of the polarization vector. The resulting shear stress deformation of the grain underneath the tip combined with the applied field effect propels polarization reversal in the adjacent grains.

160 citations


Journal ArticleDOI
TL;DR: In this article, the effect of static magnetic field on the electrolysis of copper in aqueous solution was investigated using linear sweep voltammetry, impedance spectroscopy, chronoamperometry, rotating disk voltameters, and analysis of fractal growth patterns.
Abstract: The effect of a static magnetic field, B, on the electrolysis of copper in aqueous solution is investigated using linear sweep voltammetry, impedance spectroscopy, chronoamperometry, rotating disk voltammetry, and analysis of fractal growth patterns. Data are obtained in fields of up to 6 T. There is a large enhancement of the electrodeposition rate (up to 300%) from concentrated CuSO4 solution (c ∼1 M) when pH ≤ 1. The effect of the magnetic field is equivalent to that achieved by rotating the electrode. From the pH, viscosity, field direction and concentration dependence of the field effect, the influence of field on the complex impedance, and the equivalence of field and electrode rotation, it is established that the magnetic field influences mass transport by forced convection. Convective flow is modified on a microscopic scale in the boundary layer close to the working electrode. There is no influence on the electrode kinetics. Turbulence sets in for our cell geometry when the product of field and cu...

150 citations


Journal ArticleDOI
TL;DR: In this article, the vertical type field effect transistors (FETs) are used for various organic devices because of their lowvoltage, high-current and high-speed operation.

92 citations


Journal ArticleDOI
07 Dec 2001-Science
TL;DR: Field-effect transistors based on two-component self-assembled monolayers of conjugated and insulating molecules were prepared; the conductance through them can be varied by more than three orders of magnitude by changing the applied gate bias.
Abstract: Field-effect transistors based on two-component self-assembled monolayers of conjugated and insulating molecules were prepared; the conductance through them can be varied by more than three orders of magnitude by changing the applied gate bias. With very small ratios of conjugated to insulating molecules in the two-component monolayer, devices with only a few “electrically active” molecules can be achieved. At low temperatures, the peak channel conductance is quantized in units of 2e2/h (wheree is the electron charge and h is Planck9s constant). This behavior is indicative of transistor action in single molecules. On the basis of such single-molecule transistors, inverter circuits with gain are demonstrated.

85 citations


Patent
31 May 2001
TL;DR: In this paper, the authors proposed a field effect compound semiconductor (FECS) to enhance the on-breakdown voltage of GaN compound semiconductors and improve the I-V characteristics.
Abstract: PROBLEM TO BE SOLVED: To enhance on-breakdown voltage of a GaN compound semiconductor device, and to improve the I-V characteristics. SOLUTION: A field effect compound semiconductor device comprises a GaN protective layer 4, made of an Al y Ga 1-y N (0≤y≤1) and y

81 citations


Journal ArticleDOI
22 Nov 2001-Nature
TL;DR: The transport properties of thin films of the infinite-layer compound CaCuO2 using field-effect doping is reported, showing that at high hole- and electron-doping levels, superconductivity is induced in the nominally insulating material.
Abstract: Understanding the doping mechanisms in the simplest superconducting copper oxide—the infinite-layer compound ACuO2 (where A is an alkaline earth metal)—is an excellent way of investigating the pairing mechanism in high-transition-temperature (high-Tc) superconductors more generally1,2,3,4. Gate-induced modulation of the carrier concentration5,6,7 to obtain superconductivity is a powerful means of achieving such understanding: it minimizes the effects of potential scattering by impurities, and of structural modifications arising from chemical dopants. Here we report the transport properties of thin films of the infinite-layer compound CaCuO2 using field-effect doping. At high hole- and electron-doping levels, superconductivity is induced in the nominally insulating material. Maximum values of Tc of 89 K and 34 K are observed respectively for hole- and electron-type doping of around 0.15 charge carriers per CuO2. We can explore the whole doping diagram of the CuO2 plane while changing only a single electric parameter, the gate voltage.

72 citations


Journal ArticleDOI
TL;DR: In this paper, the dependence of the gas response on the gate metal morphology of field-effect gas sensors was investigated using a scanning light pulse technique (SLPT) together with a new systematic way.
Abstract: The dependence of the gas response on the gate metal morphology of field-effect gas sensors has been investigated in a new systematic way by using a scanning light pulse technique (SLPT) together w ...

56 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of anisotropic hyperfine interactions on the recombination reactions of spin correlated radical pairs in a weak applied magnetic field are discussed in the context of the radical pair mechanism.

56 citations


Journal ArticleDOI
TL;DR: In this article, a stacked gate oxide consisting of single-erystal Gd 2 O 3 and amorphous SiO 2 was used for GaN-based metal oxide semiconductor field effect transistors.
Abstract: GaN-based metal oxide semiconductor field effect transistors (MOSFETs) were demonstrated using a stacked gate oxide consisting of single-erystal Gd 2 O 3 and amorphous SiO 2 . Gd 2 O 3 provides a good oxide/semiconductor interface and SiO 2 reduces the gate leakage current and enhances oxide breakdown voltage. Charge modulation of the n-channel depletion mode MOSFET was achieved for gate voltage from +2 to -4 V. The source-drain breakdown voltage exceeded 80 V. An intrinsic transconductance of 61 mS/mm was obtained at a gate-source and drain-source bias of -0.5 and 20 V, respectively. This is the first demonstration of epitaxial Gd 2 O 3 growth on GaN and the first use of Gd 2 O 3 as an insulating layer for nitride electronic device applications.

36 citations


Journal ArticleDOI
TL;DR: In this article, the fabrication and characterization of a ferroelectric-gate field effect transistor using Nd2Ti2O7(NTO)/Y2O3/Si structures was reported.

Patent
23 May 2001
TL;DR: In this article, a diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the VME devices was described.
Abstract: The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

Journal ArticleDOI
TL;DR: In this article, a phototransistor based on bromine-doped pentacene was proposed to reveal light detection over a wide energy range with amplification, achieving a gain of 8 nm for illumination at 632 nm.
Abstract: We have prepared phototransistors based on bromine-doped pentacene. Such devices reveal light detection over a wide energy range with amplification. The illumination modifies the charge characteristics of the Schottky gate of an enhancement-mode the metal–semiconductor field-effect transistor leading to transistor amplification of the photodiode-like response. A gain of 8 is obtained for illumination at 632 nm. These phototransistors combine the excellent properties of pentacene field-effect transistors and photovoltaic devices.

Journal ArticleDOI
TL;DR: In this paper, highmobility low-temperature (≤600°C) unhydrogenated in situ doped polysilicon thin film transistors (TFTs) are made.
Abstract: High-mobility low-temperature (≤600 °C) unhydrogenated in situ doped polysilicon thin film transistors (TFTs) are made. Polysilicon layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two polysilicon layers, the other one is fabricated from a single polysilicon layer. The electrical properties are better for transistors made of a single polysilicon layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm2 V-1 s-1) and an on/off-state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two polysilicon layers, the higher off-state current results from a field-enhanced thermal emission.

Journal ArticleDOI
TL;DR: In this paper, a negative drift field source for field effect solar cells is proposed, which is put onto a silicon layer and acts thus as an external negative drift-field source, thereby avoiding the drawbacks of ultrahigh doping.

Patent
David E. Bockelman1
22 May 2001
TL;DR: In this article, a hybrid semiconductor structure is provided, which includes a field effect transistor that may include a back gate, and the back gate is formed by providing a contact ( 506, 550 ) over a compound semiconductor region before forming an insulating layer ( 205, 508, 542, 1161 ).
Abstract: A hybrid semiconductor structure is provided. The structure may comprise a field effect transistor that may include a back gate. The back gate for a non-compound semiconductor field effect transistor may be formed by providing a contact ( 506, 550 ) over a compound semiconductor region before forming an insulating layer ( 205, 508, 542, 1161 ) and before forming the body of the field effect transistor over the compound semiconductor region. If desired, a contact ( 528, 544 ) for a back gate may also be formed after the body of the non-compound semiconductor field effect transistor is formed by forming a trench ( 526, 548 ) and depositing the contact ( 528, 544 ) in the trench ( 526, 548 ). In forming the back gate, the insulating layer ( 205, 508, 542, 1161 ) may be used as an etch-stop.

Journal ArticleDOI
TL;DR: In this paper, it was shown that voids are within the metal at the interface and, when small, are capped by the oxide film, and the rate of void growth increases with applied bias/field and tunneling current.

Journal ArticleDOI
TL;DR: In this paper, a gauge invariant quantum kinetic equation which includes impact ionization, intracollisional field effect, and collisional broadening is derived in the frame of nonequilibrium Green's functions.
Abstract: A gauge invariant quantum kinetic equation which includes impact ionization, intracollisional field effect, and collisional broadening is derived in the frame of nonequilibrium Green’s functions. We obtain analytical expressions for the impact ionization rate. For the wide band gap material ZnS, a substantial increase of the rate due to collisional broadening is obtained for moderate field strengths E⩽500 kV/cm.

Patent
22 Aug 2001
TL;DR: In this paper, the authors present a method for fabricating metal oxide semiconductor field effect transistor (MOSFET) devices with a high dielectric constant gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length that is shorter than the gate lengths.
Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length (sub-lithographic, e.g., 0.1 mum or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Patent
02 Oct 2001
TL;DR: In this paper, the mean particle diameter of polysilicon particles is evaluated by measuring the diffraction pattern of light, which can be used to adjust the field effect mobility of a thin film transistor.
Abstract: PROBLEM TO BE SOLVED: To provide a method by which the diameters of particles can be evaluated and managed nondestructively at a high speed. SOLUTION: The mean particle diameter of polysilicon particles is evaluated by measuring the diffraction pattern of light. In order to adjust the field effect mobility of a thin film transistor to >=200 cm /VS and, in addition, the in-plane fluctuation of the field effect mobility to =500 nm and the in-plane fluctuation may become <=±20%. Consequently, the diameters of the polysilicon particles can be evaluated non destructively at a high speed. In addition, a high-performance low-temperature polysilicon TFT liquid crystal device having field effect mobility which is uniformly in- plane distributed can be produced stably.

Patent
29 Jun 2001
TL;DR: In this paper, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer, and an impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate-insulating film and is contained at a high concentration in the second-layer which is not in contact to the gate.
Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Journal ArticleDOI
H.K. Gummel1, K. Singhal
TL;DR: In this article, the capacitance coefficients for metal oxide semiconductor field effect (MOSFET) based on the inversion charge relation were derived, and a simple expression was obtained for the channel charge as a function of distance.
Abstract: Intrinsic capacitance coefficients are derived for metal oxide semiconductor field effect (MOSFET) based on the inversion charge relation. A simple expression is obtained for the channel charge as a function of distance. Integrals for the proportionately partitioned source and drain-stored charges are obtained analytically. The resulting expressions are valid from deep subthreshold to strong inversion. A saturation charge q/sub mda/ is introduced that allows handling of short-channel effects. The capacitance coefficients have the required source/drain symmetry.

Patent
06 Mar 2001
TL;DR: In this paper, annealing is used to remove a surface sub-region of the initial device region, which can be further improved by epitaxially growing thereon a monocrystalline film as an improved channel layer for FET devices.
Abstract: Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After annealing, semiconductor device properties can be enhanced by removing a surface sub-region of the initial device region, and can be further improved by epitaxially growing thereon a monocrystalline film as an improved channel layer for FET devices. Such properties are relevant in MOS as well as bipolar devices.

Patent
18 Oct 2001
TL;DR: In this paper, the diode connected vertical cylindrical field effect devices (VCE devices) were described and the methods of forming the VCE devices were described. But they were not discussed in detail.
Abstract: Semiconductor diodes (320) ae diode connected vertical cylindrical field effect devices having one diode terminal (314) as the common connection between a gate (312) and a source/drain (309) of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Patent
02 Nov 2001
TL;DR: A high power transistor structure comprised of a plurality of field effect transistors fabricated in parallel on a common semiconductor chip and wherein the gate electrodes of the field effect devices are in the form of parallel finger elements having a variable pitch between the fingers which decreases uniformly or non-uniformly from a central portion of the cell to opposite outer end portions thereof as mentioned in this paper.
Abstract: A high power transistor structure comprised of a plurality of field effect transistors fabricated in parallel on a common semiconductor chip and wherein the gate electrodes of the field effect devices are in the form of parallel finger elements having a variable pitch between the fingers which decreases uniformly or non-uniformly from a central portion of the cell to opposite outer end portions thereof.

Journal ArticleDOI
TL;DR: In this paper, it was shown that the inductive effect does not fit the experimental data on the transmission of electrical effects in a range of chemical reactions and in infrared stretching frequencies.

Journal ArticleDOI
TL;DR: In this paper, the development of ion sensitive field effect capacitors (ISFEC) as microsensors was reported, which improved the sensitivity of field effect transistor (FET)-based chemical sensors.
Abstract: This paper reports on the development of ion sensitive field effect capacitors (ISFEC) as microsensors. ISFEC/(metal/oxide/semiconductor) field effect transistor (MOSFET) amplifying structures are designed and studied in order to improve the sensitivity of field effect transistor (FET)-based chemical sensors (CHEMFETs). Demonstration is performed through the characterisation of SiO2/Si3N4 ISFEC sensors for pH measurement. Linear responses and high detection sensitivities are evidenced on wide pH ranges. Theoretical and experimental studies are in agreement, clarifying dynamic phenomena, lower experimental amplification ratios and measurement drawbacks. Such amplifying structures will lead to further improvements for FET-based microsensors.

Journal ArticleDOI
TL;DR: In this paper, the current and voltage characteristics of a field effect transistor are described using experimental data derived from a Radiant Technologies FFET, and the drain current is measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor.
Abstract: There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Patent
02 May 2001
TL;DR: In this article, a photolithographic process is used for the fabrication of a field effect transistor (FET) and a soluble amorphous active semiconductor material is deposited over the first electrode (2) and the vertical step (6) such that a vertically oriented transistor channel between the drain and source electrodes (2, 5) is obtained.
Abstract: A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the substrate (1). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes (2, 5) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode (4) the gate electrode of the field-effect transistor. Over the layers in the vertical step (6) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode (8) directly or indirectly and forming a vertically oriented transistor channel (9) of the p or n type between the first (2) and the second (5) electrode. In a method for fabrication of a field effect transistor a vertical step (6) is formed by a means of a photolithographic process and a soluble amorphous active semiconductor material (8) is deposited over the first electrode (2) and the vertical step (6) such that a vertically oriented transistor channel between the drain and source electrode (2, 5) is obtained. In a JFET the semiconductor material (8) contacts the gate electrode (4) directly. In a MOSFET a vertically oriented gate isolator (7) is provided between the gate electrode (4) and the semiconductor material (8).

Journal ArticleDOI
TL;DR: In this paper, the Laplace and Poisson equations were solved analytically using a sequence of three conformal mapping transformations, and it was shown that the V-groove geometry is much more effective than the corresponding planar geometry.
Abstract: Inducing charge into V-groove quantum wires via a field effect from a back gate is investigated by solving the Laplace and Poisson equations analytically, using a sequence of three conformal mapping transformations These solutions show that the V-groove geometry is much more effective than the corresponding planar geometry Induced charge densities of order 108 m-1 are well within present growth and processing capabilities and offer the prospect of clean, high-conductivity devices without the need for modulation doping