Field effect

About: Field effect is a research topic. Over the lifetime, 4018 publications have been published within this topic receiving 92613 citations.

Using thin film transistors to quantify carrier transport properties of amorphous organic semiconductors

Abstract: The hole transport properties of two phenylamine-based compounds were evaluated by thin film transistor (TFT) measurement and time-of-flight (TOF) technique. The compounds were N,N′-diphenyl-N,N′-bis(1-naphthyl) (1,1′biphenyl)-4,4′diamine (NPB) and 4,4′,4″-tris[n-(2-naphthyl)-n-phenyl-amino] triphenylamine (2TNATA). With tungsten oxide/gold as the charge injecting electrode, the field effect mobility of NPB was found to be 2.4×10−5cm2∕Vs at room temperature, which was about one order of magnitude smaller than that obtained from independent TOF experiments (3×10−4cm2∕Vs). Similar observations were found for 2TNATA. Temperature dependent measurements were carried out to study the energetic disorder of the materials. It was found that the energetic disorder was increased in the neighborhood of a gate dielectric layer.

Power field effect devices having small cell size and low contact resistance

Abstract: A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this high conductivity layer allows a substantially smaller contact window to be employed for making contact between the final metallization and the source region. As a consequence, the aperture in the gate electrode and the cell size of the device can both be substantially reduced. The device has substantially improved operating characteristics. A method of producing the device is also described.

Field effect device with polycrystalline silicon channel

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Semi-insulating bulk GaAs thermal neutron imaging arrays

Abstract: Prototype thermal neutron imaging arrays have been fabricated from semi-insulating (SI) bulk GaAs. The arrays are 1 mm square Schottky diodes arranged in a 5/spl times/5 matrix. GaAs Schottky barrier radiation detectors are relatively radiation hard and can withstand higher neutron and gamma ray exposure fields than MOS-based Si diode imaging arrays. The devices use /sup 10/B to convert incident thermal neutrons to energetic Li ions and alpha particles. The truncated field effect observed with SI bulk GaAs detectors produces high and low field regions in the device. Electron-hole pairs produced in the active (or high field) region of the device contribute to the observed induced charge, whereas electron-hole pairs produced in the low field region contribute very little to the induced charge. The effect is manipulated to reduce the background gamma ray interaction rate in the devices. Preliminary results show no indication of device degradation after exposure to a total thermal neutron fluence of 1.73/spl times/10/sup 13/ n/cm/sup 2/. Images have been formed of 1, 1.5, and 2 mm holes and crosses from 2 mm thick Cd templates.

High performance top-gated multilayer WSe2 field effect transistors

Abstract: In this paper, high performance top-gated WSe2 field effect transistor (FET) devices are demonstrated via a two-step remote plasma assisted ALD process. High-quality, low-leakage aluminum oxide (Al2O3) gate dielectric layers are deposited onto the WSe2 channel using a remote plasma assisted ALD process with an ultrathin (~1 nm) titanium buffer layer. The first few nanometers (~2 nm) of the Al2O3 dielectric film is deposited at relatively low temperature (i.e. 50 ?C) and remainder of the film is deposited at 150 ?C to ensure the conformal coating of Al2O3 on the WSe2 surface. Additionally, an ultra-thin titanium buffer layer is introduced at the WSe2 channel surface prior to ALD process to mitigate oxygen plasma induced doping effects. Excellent device characteristics with current on?off ratio in excess of 106 and a field effect mobility as high as 70.1 cm2 V?1 s?1 are achieved in a few-layer WSe2 FET device with a 30 nm Al2O3 top-gate dielectric. With further investigation and careful optimization, this method can play an important role for the realization of high performance top gated FETs for future optoelectronic device applications.