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Field effect

About: Field effect is a research topic. Over the lifetime, 4018 publications have been published within this topic receiving 92613 citations.


Papers
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Patent
11 Feb 1988
TL;DR: In this paper, a power insulated-gate field effect transistor and a control semiconductor element are formed in a common semi-conductor substrate. But unlike the case where these respective elements are integrated separa-tely into a common semiconductor substrate, the case in this paper is different.
Abstract: A semiconductor device is provided which includes a power insulated-gate field effect transistor and a control semiconductor element formed in a common semi­conductor substrate (18) A first area (27) is so formed as to provide a drain region of low resistance in the insulated-gate field effect translator and made in resistivity different than a second region (24a, 24b) where the control semiconductor element is formed It is thus possible to integrate respective elements in a common semiconductor substrate (18), unlike the case where these respective elements are integrated separa­tely into a common semiconductor substrate

46 citations

Journal ArticleDOI
TL;DR: High-performance operationally stable organic field-effect transistors were successfully fabricated on a PowerCoat HD 230 paper substrate with a TIPS-pentacene:polystyrene blend as the active layer and poly(4-vinylphenol)/HfO2 as the hybrid gate dielectric and exhibited remarkable stability under effects of gate bias stress and large number of repeated transfer scans with negligible performance spread.
Abstract: High-performance operationally stable organic field-effect transistors were successfully fabricated on a PowerCoat HD 230 paper substrate with a TIPS-pentacene:polystyrene blend as the active layer and poly(4-vinylphenol)/HfO2 as the hybrid gate dielectric. The fabricated devices exhibited excellent p-channel characteristics with a maximum and av field effect mobility of 0.44 and 0.22(±0.11) cm2 V–1 s–1, respectively, av threshold voltage of 0.021(±0.63) V, and current on–off ratio of ∼105 while operating at −10 V. These devices exhibited remarkable stability under effects of gate bias stress and large number of repeated transfer scans with negligible performance spread. In addition, these devices displayed very stable electrical characteristics after long exposure periods to humidity and an excellent shelf life of more than 6 months in ambient environment. Thermal stress at high temperatures however deteriorates the device characteristics because of the generation and propagation of cracks in the active ...

46 citations

Proceedings ArticleDOI
01 Dec 2006
TL;DR: In this paper, the authors have successfully fabricated amorphous Ga 2O3-In2O3 -ZnO thin film transistor (TFT) with excellent electrical properties and good stability under constant current stress.
Abstract: We, for the first time, have successfully fabricated amorphous Ga 2O3-In2O3-ZnO thin film transistor (TFT) with excellent electrical properties and good stability under constant current stress. This transistor shows a field effect mobility of 10 cm2/Vs, an off current below 2 pA and a drain current on-to-off ratio of above 108. The threshold voltage shift was less than 0.2 V for 100 hours at 3 muA and 60 degC. Such stable oxide transistors can be utilized as driving transistor for large area OLED display

46 citations

Journal ArticleDOI
TL;DR: In this article, the steady-state and transient behavior of PANi-FETs was investigated by comparing the metal-oxide-semiconductor field-effect transistor threshold voltage to the polyaniline gate field effect transistor (PANi)-FET threshold voltage.

46 citations

Journal ArticleDOI
TL;DR: In this paper, gate tunable p-type multilayer tin mono-sulfide (SnS) field effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performances.
Abstract: Gate tunable p-type multilayer tin mono-sulfide (SnS) field-effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performances. The devices showed anisotropic inplane conductance and room temperature field effect mobilities ~5 - 10 cm$^2$/Vs. However, the devices showed appreciable OFF state conductance and an ON-OFF ratio ~10 at room temperature. The weak gate tuning behavior in the depletion regime of SnS devices is explained by the finite carrier screening length effect which causes the existence of a conductive surface layer from intrinsic defects induced holes in SnS. Through etching and n-type surface doping by Cs2CO3 to reduce/compensate the not-gatable holes near SnS flake's top surface, the devices gained an order of magnitude improvement in the ON-OFF ratio and hole Hall mobility ~ 100 cm$^2$/Vs at room temperature is observed. This work suggests that in order to obtain effective switching and low OFF state power consumption, two-dimensional (2D) semiconductor based depletion mode FETs should limit their thickness to within the Debye screening length of carriers in the semiconductor.

46 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20235
202210
202171
202078
2019103
2018133