Showing papers on "Field-effect transistor published in 1968"

Modeling and simulation of insulated-gate field-effect transistor switching circuits

Abstract: A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.

SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain

Abstract: Insulated-gate field-effect transistors using Schottky barrier contacts for the source and drain have been studied. At room temperature, the device characteristics are Comparable to conventional IGFET's with similar electrode geometry. At lower temperatures, the current transport is by tunneling of carriers from the metal across the Schottky barrier to the semiconductor inversion layer.

High voltage integrated circuit transistor

Abstract: TERING NORMAL COLLECTOR-EMITTER BREAKDOWN, BECAUSE THE FIELD INTENSITY IN THE COLLECTOR-BASE CHARGE LAYER IS LIMITED. AN INTEGRATED CIRCUIT TRANSISTOR INCLUDES A SUBSTRATE AND AN EPITAXIALLY GROWN SEMICONDUCTOR MATERIAL THEREON PROVIDING A THREE-LAYER TRANSISTOR COMPRISING A COLLECTOR LAYER, AN EMITTER LAYER, AND A BASE LAYER THEREBETWEEN. THE COLLECTOR LAYER IS CHARACTERIZED BY VIRTUALLY COMPLETE DEPLETION OF MAJORITY CARRIERS AT A COLLECTOR-EMITTER VOLTAGE LESS THAN THE VOLTAGE AT WHICH COLECTOR-EMITTER BREAKDOWN WOULD OTHERWISE OCCUR. AS A RESULT, THE COLLECTOR-EMITTER VOLTAGE MAY BE INCREASED WITHOUT ENCOUN-

Characteristics of thermal annealing of radiation damage in MOSFET's.

Abstract: Thermal annealing characteristics of electron radiation damage in p-channel MOSFET, noting time and temperature dependence and activation energy

ZnO field-effect transistor

Abstract: Fabrication of experimental insulated-gate field-effect transistors on single crystal ZnO is described. Measured transconductance of 10 µmhos is two orders of magnitude smaller than that predicted for this structure by the Hall mobility of 220 cm2/V ċ s. Threshold voltage indicates relatively large values of surface states and/or insulator charge.

MOS field effect transistors formed by gate masked ion implantation

Abstract: MOS enhancement mode field effect transistors with a circular geometry and with drains offset from the gate by distances from 0.1 mil to 0.9 mil were implanted with boron ions to fill in the offset region and thus achieve perfect alignment (i.e., no overlap) between gate and drain. The energies used were 50 to 100 keV and a 4000 A-thick aluminum gate acted as a mask to prevent ions from penetrating into the channel region. The best junctions were obtained with 100-keV ions, with the sheet resistances being typically 4000 ω/□ for the implanted region. This additional drain resistance was quite small compared to the channel resistance of the devices and so was not objectionable. Ordinary diffused MOSFET's were included on the same wafers for comparison with the ion implanted MOSFET's. It was found that the differences in noise, leakage, and drain breakdown voltage were not serious. The chief advantage of the ion implanted MOSFET is the extremely low feedback capacitance due to the lack of gate-drain overlap, but this advantage is difficult to exploit in a conventional package because of the package capacitance. However, a significant difference was noted in switching characteristics between diffused and ion implanted MOSFET's mounted on TO-18 headers.

Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates☆

Abstract: Silicon insulated-gate field-effect transistors (FETs) have been fabricated by processes involving relatively non-critical photoresist and self-limiting etching steps. Important features of the method include the formation of the gate insulator under extremely clean conditions, incorporation of an alkali ion barrier (silicon nitride) to achieve stable device characteristics and automatic alignment of the gate electrode with respect to source and drain. The gate insulator, comprising 600 A of grown silicon dioxide covered with 400 A of silicon nitride, is formed at the beginning of fabrication. Thus, the SiSiO2 interface is established at a point where the best state-of-the-art cleaning techniques can be applied to the starting material. A thick (8000 A) layer of SiO2 is pyrolytically deposited over the nitride to minimize contact capacitances in the finished structure. This must be removed from the active device region, and advantage is taken of the difference in etch rate between SiO2 and silicon nitride to ensure a well-controlled gate insulator thickness. Thus the nitride layer serves the dual function of providing a barrier to mobile ions in the completed structure, and of acting as an etch-resistant layer during fabrication to achieve control over geometry. A polycrystalline layer of silicon is used to form the gate electrode, which is shaped early in the process, and is used to define the limits of the source and drain windows. This aspect of the fabrication assures self-alignment of the gate electrode with respect to source and drain. During the diffusion of source and drain regions the polycrystalline silicon is rendered sufficiently conductive that no metallization of the gate electrode is required, except at one end for contacting purposes. This eliminates the need for a critical photoresist alignment. Both n and p induced-channel (enhancement) devices have been made with this process. Turn-on voltages at 10 μA drain current of +1.35 V (n-channel) and −2.6 V (p-channel) with less than 12 per cent spread over a slice were obtained. Analysis of the device characteristics indicates field-effect mobilities of 335 and 233 cm2/V-sec for the n- and p-channel devices respectively. Aging behavior under bias at 300°C indicates the presence of residual mobile positive charge of the order of 1.5 × 1011 charges/cm2, resulting in turn-on voltage shifts of less than 1 V over several hundred hr with +10 V applied to the gate.

Al2O3‐SILICON INSULATED GATE FIELD EFFECT TRANSISTORS

Abstract: MOS transistors, with aluminum oxide as gate insulator, have been fabricated. The Al2O3 films were formed by first depositing aluminum on freshly cleaned 10 Ω‐cm silicon and then anodizing the aluminum in an oxygen plasma. All other steps used standard silicon technology. Electron diffraction showed that the insulator films are amorphous. The index of refraction is between 1.67 and 1.70 and the relative dielectric constant is 7.6. The devices have a threshold voltage of between ±0.5 V, and an interface state density of about 2 × 1010 states/cm2‐eV. No evidence for ionic motion under positive bias was found at elevated temperatures. Under 1 MeV electron bombardment at various fluence levels and bombardment biases these devices showed excellent radiation resistance. Their radiation behavior is better than that observed for MNS or ``hardened SiO2'' devices.

Apparatus for stabilizing field effect transistor thresholds

Abstract: Apparatus is disclosed which permits the adjustment and stabilization of field effect transistor threshold voltages so that the variation in threshold voltages due to fabrication nonuniformities are reduced to a minimum. This is accomplished by utilizing one of a plurality of field effect devices on a semiconductor chip as a sensor to detect changes in the characteristics of the devices, from whatever cause. A feedback circuit provides a signal which adjusts the voltage applied to the semiconductor chip or substrate and returns the threshold voltage to some nominal value. Several circuit arrangements are shown which accomplish the desired result. A plurality of chips each having a sensor and associated feedback circuitry is also disclosed indicating the environment in which the concept of the present invention is used most advantageously.

Non-destructive readout of ferroelectrics by field effect conductivity modulation

Abstract: CdSe thin film field effect transistors (TFFET) have been deposited by vacuum evaporation on BaTiO3 crystals which can be switched from depletion to enhancement-only operation by switching the ferroelectric substrate. CdSe resistors on BaTiO3 gave two state resistors with resistance ratios of 100 1 obtainable. The efficiency of the devices was nevertheless much less than is theoretically possible. This was due to trapping near the BaTiO3/CdSe interface. A uniform distribution in energy of traps would give the observed dependence of conductance change on initial conductivity.

Semiconductor integrated circuit having mis and bipolar transistor elements

Abstract: MIS and bipolar transistor elements are provided within a unitary body of semiconductor material wherein first and second regions of opposite conductivity type to that of the substrate provide source and drain regions between which is positioned an insulated gate electrode for the MIS transistor while in a region that may be the same as one of the source and drain regions or an additional region, elements of the bipolar transistor are provided with utilization of the substrate as a collector region or by having laterally disposed emitter and collector regions in a base region.

MOSFET operation at 4.2 K.

Abstract: MOSFETS operate at 4.2 K and act as impedance transformers for high impedance (1010Ω) ir detectors. Several types, both n‐channel and p‐channel, have operated successfully at this temperature and withstood the thermal shock of repeated cycling from room temperature. Low device power dissipation and relatively low noise can be achieved by optimizing drain current (ID) and drain‐to‐source voltage (VDS) for the particular device. Power dissipations as low as 0.4 mW have been recognized.

Schottky-barrier field-effect transistor

Abstract: A Schottky-barrier field-effect transistor is disclosed with a semiconductor channel of relatively low conductivity between the source and drain electrodes which may be electrically influenced by a Schottky-barrier gate electrode located on the semiconductor channel. The transistor is characterized by a zone or region of higher conductivity which extends from the vicinity of the source electrode to near the gate electrode. Further, source and drain regions are conveniently provided for the transistor of semiconductor of the same conductivity type as the channel semiconductor at the Schottky-barrier electrode. Advantageously, the drain region may be made of semiconductor of high conductivity and the same conductivity type as the source region. The high conductivity region may be achieved through either diffusion or epitaxial growth technique.

Semiconductor circuit devices using insulated gate-type field effect elements having protective diodes

Abstract: Insulated gate-type field effect transistors used in capacitive memory circuits and having protective diodes for protecting the insulating films below the gate electrodes from electrical breakdown, in which parasitic transistor action which might be caused by minority carriers injected into semiconductor substrates by noise signals applied to the protective diodes are eliminated by means for suppressing the injection of minority carriers or by means for preventing injected minority carriers from reaching the drain regions of the field effect transistors.

A new insulated gate tetrode with high drain breakdown potential and low miller feedback capacitance

Abstract: Insulated gate field effect transistors (IGFET's) with the gate offset from the drain electrode exhibit high drain breakdown potential and very low Miller feedback capacitance. The new insulated gate tetrode (IGT) described in this paper utilizes a second stacked gate to create the offset channel. The main advantage is the possibility of optimizing the device performance, especially the drain breakdown potential for both P -and N -channel devices. Considered in the paper are design and fabrication problems, V-I characteristics, drain breakdown potential, dynamic drain resistance, small-signal equivalent circuit, and large-signal limitations. P -channel IGT's with drain breakdown potentials up to 300 V have been built. The design of the IGT depends mainly on the tradeoff between drain breakdown potential and the limited frequency response caused by the time constant of the offset channel. The results to date indicate that the IGT has a large drain voltage range and an extremely low Miller feedback capacitance and is adaptable to different operating conditions. The IGT appears very promising for use in power amplifiers and switching applications.

Semiconductor device and a method of making the same

Abstract: Semiconductor device of the field effect transistor type including a first semiconductor region of one conductivity type, a second semiconductor region abutting the first region and containing at least one polycrystalline region and one single crystal region, the polycrystalline region having a conductivity type opposite to that of the first semiconductor region thereby forming a PN junction therealong, and a third semiconductor region formed in the second semiconductor region.

Semiconductor switching circuits and integrated devices thereof

Abstract: A switching circuit with small consuming power and highswitching speed, in which a bipolar transistor and a resistor are connected in the emitter follower configuration to the output terminal of insulated gate-type field effect transistors in complementary connection.

Transistor switch with minimized transition power absorption

Abstract: A transistor switch, an inductor and the load are serially connected so that during turn-on transition of the transistor, the inductor holds back current flow until the transistor is saturated. A capacitor paralleled around the transistor charges during turnoff transition so that current through the transistor during transition is minimized to minimize power absorption therein.

Field effect transistors for integrated circuits and methods of manufacture

Abstract: P-channel field-effect transistors are described which include a silicon substrate with an N-type epitaxial layer on one face thereof and an N-type subepitaxial diffused region which extends in one direction into a P-type region in the face of the substrate and in the opposite direction into the epitaxial layer to form a junction with a P-type diffused channel region extending partially into the epitaxial layer. These P-channel transistors may constitute a portion of an integrated circuit including a complementary N-channel field effect transistor and/or vertical and surface bipolar NPN and PNP transistors and resistors. Processes are disclosed for forming such transistors wherein a P-type diffusion in an epitaxial layer and an N-type diffused subepitaxial region are further diffused to form a junction therebetween.

Theoretical threshold voltages for MOS field effect transistors

Abstract: By employing the charge neutrality condition in the vicinity of the gate insulator in the MOS structure, theoretical curves of the threshold voltages for both n- and p-channel MOSFETs are obtained as a function of substrate doping concentration, built-in positive charge at the oxide-silicon interface, oxide thickness, and surface trapping. Curves of theoretical threshold voltages for MOSFETs employing Al2O3-SiO2 gate insulators are also obtained. The effect of gold doping of the silicon substrate upon the threshold voltages of MOSFETs is discussed. As a result, the conditions which determine whether a particular MOSFET will be a depletion type or an enhancement type are specified as a function of the construction parameters of the device.

Field effect transistor having passivated gate insulator

Abstract: An insulated-gate field effect transistor is described which includes a gate insulator defined as a laminate structure comprising a phosphosilicate glass (PSG) layer and a silicon dioxide (SiO2) layer, the ratio of the thicknesses of such layers and, also, the P2O5 concentration in the PSG layer being properly chosen to insure stable device characteristics over extended periods under operation conditions.

An insulated gate type field effect semiconductor device having a breakdown preventing element

Abstract: An MOS field effect transistor comprising an N-type semiconductor substrate having a P type diffused region formed therein which is more shallow than a P type source and a P type drain diffused regions, the shallow diffused region being connected to a gate electrode by a conductive means, and utilizing the breakdown phenomenon of a PN junction formed between the shallow diffused region and the substrate thereby to prevent the breakdown of an insulating layer under the gate electrode.

Breakdown preventing circuit and an integrated device thereof for a semiconductor device having an insulate gate electrode

Abstract: A circuit and an integration thereof for preventing the breakdown of an oxide film in an MOS type field effect transistor, wherein a resistor is connected between a metal gate electrode and a protecting diode (clamp diode)

Field-effect integrated circuit and method of fabrication

Abstract: An integrated circuit operating at about 77 DEG K. having first and second field effect transistors, a digital terminal being connected to the source of each transistor and capacitively coupled to the drain of the first transistor and the gate of the second transistor. A first read terminal is connected to the drain of the second transistor and capacitively coupled to the drain of the first transistor while a second read terminal is capacitively coupled to the drain of the first transistor. The method of fabrication makes use of stray capacitance in the laying of the layers.

Photodiode preamplifier circuit for a card reader system

Abstract: A photodiode preamplifier circuit including input terminals to which a photodiode may be connected. The photodiode senses the presence of a mark or a hole on a sense card and in turn provides a change in voltage at a control transistor to which the photodiode is connected. An output transistor is connected to the control transistor and is conductively controlled by the signal applied to the control transistor to in turn provide an output signal at one or the other of two binary levels. A reference level control means is connected between the control transistor and the input terminals of the amplifier and responds to current variations in the control transistor to produce a compensating current to the photodiode. This compensating current maintains a constant DC voltage level with reference to a constant threshold level at the output transistor.

Junction Field-Effect Transistors

Abstract: The field effect transistor was proposed by Julius Lilienfeld in US patents in 1926 and 1933 (1,900,018). Moreover, Shockley, Brattain, and Bardeen were investigating the field effect transistor in 1947. Though, the extreme difficulties sidetracked them into inventing the bipolar transistor instead. Shockley's field effect transistor theory was published in 1952. However, the materials processing technology was not mature enough until 1960 when John Atalla produced a working device.