Showing papers on "Field-effect transistor published in 1970"

Microwave properties of Schottky-barrier field-effect transistors

Abstract: The microwave properties of silicon Schottky-barrier field-effect transistor(MESFET'S) with a gate-length of one micrometer are investigated. The scattering parameters of the transistors have been measured from 0.1 GHz up to 12 GHz. From the measured data an equivalent circuit is established which consist of an intrinsic transistor and extrinsic elements. Some of the elements of the intrinsic transistor, notably the transconductance, are strongly influenced by the saturation of the drift velocity. Best performance of the intrinsic transistor is obtained with highly doped and thin channels. The measured power-gain is in good agreement with theoretical values deduced from the equivalent circuit. The best device has a maximum frequency of oscillation fmax of 12 GHz. The investigation reveals that the extrinsic elements, especially the resistance of the gate-metallization and the gate-pad parasitics, degrade the power-gain considerably. Without them a value of fmax close to 20 GHz is predicted.

Computer aided two-dimensional analysis of the junction field-effect transistor

Abstract: A two-dimensional analysis is presented of the mechanisms of operation for a junction field-effect transistor. Particular emphasis is placed upon the process of electric current saturation in both wide gate and narrow gate structures. It is shown that velocity saturated carrier transport in a source-drain channel produces heretofore unreported mechanisms of device operation. Comparisons made between the conclusions derived from this two-dimensional analysis and the conventional one-dimensional theory of JFET operation are presented in graphic form.

Quantum mechanical calculation of the carrier distribution and the thickness of the inversion layer of a MOS field-effect transistor

Abstract: The carrier distribution in the inversion layer of a MOS-structure at room temperature was calculated assuming a quantization of the allowed energy levels at the surface and a linear electrostatic potential. It was found that for strong inversion the carrier distribution deviates considerably from the one found by using classical statistics but approaches the classical limit for weak inversion when many electric subbands are occupied. A new definition for the channel thickness was introduced based on the integrated charge in the channel and compared to other definitions. Channel thicknesses so defined range from 30 to 400 A for practical devices depending on surface potential. The integrated charge in the channel deviated little from the one found using classical statistics.

A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide

Abstract: Results of an experimental study are reported of a new instability found in p- and n-channel MOS transistors. This phenomenon is that when a higher voltage in an excess of a brakdown voltage is applied to the drain electrode the breakdown voltage drifts to a higher value and the drain current also increases. The origin of this instability is investigated by extensive measurements and analyses of the electrical characteristics of the transistors. It is concluded that 1) the semiconductor surface near the drain becomes p-like in the p-channel transistors and n-like in the n-channel transistors and thus the active channel length is shortened, 2) this is caused by charging of the gate oxide due to injection of electrons or holes generated during the drain avalanche breakdown, and 3) electron and hole injection is much affected by electric field across the oxide over the drain junction.

Floating gate transistor and method for charging and discharging same

Abstract: A floating gate transistor comprising a floating silicon or metal gate in a field effect transistor which is particularly useful in a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO2 is charged by transferring charged particles (i.e., electrons) across the insulation from the substrate during an avalanche (breakdown) condition in the source or drain junctions of the transistor.

Field effect semiconductor device with memory function

Abstract: A field effect transistor is provided with a gate assembly comprising a sandwich of a layer of silicon oxide with excess silicon between two insulating films of appropriate thickness for the entrapment of charge carriers in the silicon-rich silicon oxide layer. Such entrapment provides the transistor with information storage capabilities in which information can be stored for a long time and readily erased or modified.

Dynamic performance of Schottky-barrier field-effect transistors

Abstract: The dynamic performance of Schottky-barrier field-effect transistors is discussed, with the aim of finding in a most simple way the physical parameters on which the dynamic properties of a FET depend, how strong they influence the dynamic qualities of FET'S, and what recommendations can be given as to proper choice of material or structure for FET'S with good high-frequency performance.

High-speed gallium-arsenide Schottky-barrier field-effect transistors

Abstract: The letter shows that gallium arsenide is a well suited material for high-frequency field-effect transistors. From preliminary measurements on realised transistors, it is shown that the frequency limit for power amplification is considerably higher than for other known transistors. The processes involved are briefly described.

Mos fet reference voltage supply

Abstract: A means for obtaining regulated reference supply voltages substantially at one or more integral multiples of the threshold voltage (Vt) of field effect transistors fabricated completely with field-effect-transistors on a single monolithic integrated circuit chip.

Charge sensing circuit

Abstract: A first field effect transistor is turned on during a first phase recurring interval for charging a first capacitor at the gate electrode of an output field effect transistor. During a second phase recurring interval, a second field effect transistor in series between the plate of a second capacitor and the first capacitor, is turned on. The voltage on the first capacitor is connected to the plate of the second capacitor for inverting or depleting the semiconductor region subjacent the plate of the second capacitor. If minority carriers are available in the semiconductor substrate adjacent to the region covered by the plate, the subjacent region is inverted and electrically connected to a charge coupled circuit. If an inversion does not occur, the voltage on the first capacitor is unchanged and the output field effect transistor remains on for indicating the absence of charge (minority carriers) on the charge coupled circuit. If the charge coupled circuit provides minority carriers to the second capacitor, the voltage on the first capacitor is reduced and the output field effect transistor is turned off for indicating the presence of charge on the charge coupled circuit.

On the influence of hot carrier effects on the thermal noise of field-effect transistors

Abstract: The noise resistance of the field-effect transistor has been calculated taking into account high-field effects such as mobility saturation and hot carrier temperature upon the thermal noise. The result of the calculations can be represented by a practical formula. The calculated results have been compared with measurements of the noise of a junction gate FET and a MOS tetrode with short active channels. The agreement is reasonable. At room temperature the effect is moderate, but at low temperatures it is considerable.

Nonvolatile flip-flop memory cell

Abstract: The present invention relates to a nonvolatile flip-flop memory cell in which an alterable threshold voltage nonvolatile MNOS field effect transistor is connected to each bistable terminal of a volatile flip-flop circuit. The nonvolatile MNOS field effect transistors nonvolatilely retain the state of the volatile flipflop circuit during a power failure to the flip-flop circuit. During the power failure to the volatile flip-flop circuit, the threshold voltage of one of the nonvolatile MNOS field effect transistors is changed, to nonvolatilely retain the state of the volatile flip-flop circuit. The state of the flip-flop circuit is reset when power is restored, with the aid of the nonvolatile MNOS field effect transistors. When a power failure to the volatile flip-flop circuit is sensed, a high negative potential is applied to the gates of the nonvolatile MNOS transistors to change the threshold of the nonvolatile MNOS transistor which is connected to the zero potential terminal of the volatile flip-flop circuit. The state of the volatile flip-flop circuit is retained in said nonvolatile MNOS field effect transistors. The binary bit of information nonvolatilely stored in the nonvolatile memory cell is read back into the volatile flip-flop circuit when power is restored.

Fabrication of insulated gate field-effect transistors involving ion implantation

Abstract: An insulated gate field-effect transistor is made which utilizes both Schottky barrier connections and ion-implanted zones. The resultant structure incorporates source and drain zones, which are formed by ion implantation and whose spacing is fixed by the gate electrode, and source and drain electrodes which make ohmic connection to the implanted source and drain zones and rectifying connections to unimplanted material.

Stabilized complementary micro-power square wave oscillator

Abstract: A square wave oscillator is shown utilizing a P channel and an N channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) in combination with a quartz crystal for generating a frequency stabilized square wave signal suitable for use in a wristwatch.

Input transient protection for complementary insulated gate field effect transistor integrated circuit device

Abstract: In a CMOS integrated circuit of the type which includes a diffused P type region in which the N type transistors are formed, a resistor-region is provided by diffusion at the same time as that P type region. A diode having low breakdown is established by forming P+ type regions or N+ type regions in electrical communication with the resistor so that the diode breakdown is effectively dominated by the impurity concentration characteristics of the P+ type or N+ type regions.

Theory of the thin-oxide m.n.o.s. memory transistor

Abstract: A general model for the transient behaviour of m.i.s. memory transistors is presented. The model is applied to a practical memory transistor which has an insulator layer consisting of 500–1000 A silicon nitride on 15–25 A silicon dioxide. The properties of this device are calculated and are shown to agree with experimental data.

Anomalous noise behavior of the junction-gate field-effect transistor at low temperatures

Abstract: Measurements are reported on the noise resistance and the noise conductance of the junction-gate FET in the temperature range 77°K-400°K. At low temperatures anomalous noise behavior has been observed. The measurements are discussed in the light of existing theories and, when necessary, the theoretical model has been extended. The agreement is satisfactory. Generally the extra noise is caused by mobility saturation, increased free-carrier temperature, free-carrier trapping and multiplication effects in the pinched-off region. Finally, several applications are discussed in relation to the limiting noise sources.

Complementary insulated gate field effect devices

Abstract: A complementary pair of insulated gate field effect transistors is fabricated in a monocrystalline silicon wafer. The method features the use of doped-oxide diffusion sources, self-aligned, passivated-gate electrodes, and the concurrent diffusion of the source and the drain regions for both the n-channel device and the p-channel device in a single step.

Semiconductor device with a field effect transistor

Abstract: A semiconductor device includes a common substrate, on the one side of which there are provided an insulated gate field effect transistor and bipolar transistor for protecting the former transistor from the failure. The gate of the former is electrically connected to the emitter of the latter to have the same potential.

Process for producing self aligned gate field effect transistor

Abstract: This disclosure relates to a process for preparing a self-aligned gate field effect transistor in which the source-drain spacing is automatically held to a minimum as a result of the processing steps.

An analysis of current saturation mechanism of junction field-effect transistors

Abstract: A two-dimensional numerical analysis has been amde for junction field-effect transistors with small and large values of length-to-width ratio. Comparison of the results for different drain bias voltages shows the cause of the saturation of the drain current and the finite differential drain conductance in the saturation region. The effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified. Detailed pictures of the free carrier density distribution are presented, and the minimum channel width and the channel length are given for various bias conditions. A conduction path from the source to the drain with appreciable free carrier density has been found for bias conditions normally considered as pinched-off conditions. The drain characteristic with gate bias voltage is seen to be equivalent to that of a device with correspondingly smaller width and zero gate bias.

Circuitry for distinguishing between background and intelligence areas on a document

Abstract: In a facsimile system, apparatus for automatically adjusting the gain of a circuit connected to a document scanning photoreceptor so that information signals may be readily separated from the various shades of background reflected from the document being scanned. The apparatus includes an operational amplifier, the feedback loop of which, in a first embodiment, includes a field effect transistor. The gain of the operational amplifier is adjusted so that its output is at one of two levels, representing information or background signals, by controlling the signal applied to the gate electrode of the field effect transistor. In a second embodiment the effective load resistor of the photoreceptor is varied by interposing a field effect transistor between the photoreceptor and the input of the operational amplifier. The amplitude of the output signal of the operational amplifier is adjusted by controlling the signal applied to the gate electrode of the field effect transistor.

Method of making complementary field-effect transistors by single step diffusion

Abstract: D R A W I N G COMPLEMENTARY N-CHANNEL AND P-CHANNEL FIELD-EFFECT TRANSISTORS ARE FORMED ON A SINGLE CONDUCTIVITY-TYPE SEMICONDUCTOR WAFER BY A SINGLE DIFFUSION STEP AND A SINGLE PATTERNING STEP WHICH SEPARATES THE N-CHANNEL FROM THE P-CHANNEL DEVICES. IN ONE EMBODIMENT, COMPLEMENTARY DEVICES ARE MADE BY FORMING AN APPROPRIATE PATTERN IN A CONDUCTING AND AN INSULATING FILM OVERLYING A SEMICONDUCTOR WAFER OF A FIRST CONDUCTIVITY TYPE, DEPOSITING AN OPPOSITE CONDUCTIVITY TYPE INDUCING IMPURITY-DOPED INSULATING FILM OVER THE PATTERNED WAFER, DEPOSITING A FIRST CONDUCTIVITY TYPE INDUCING IMPURITY-DOPED INSULATING FILM OVER THE FIRST FILM, REMOVING THE IMPURITY-DOPED FILMS FROM ONE PORTION OF THE WAFER, DEPOSITING AN OPPOSITE CONDUCTIVITY TYPE INDUCING IMPURITY-DOPED INSULATING FILM OVER THE ENTIRE WAFER, DIFFUSING THE IMPURITIES INTO THE WAFER TO FORM SOURCE AND DRAIN REGIONS FOR ONE TRANSISTOR AND SOURCE, DRAIN AND A CHANNEL REGION FOR THE COMPLEMENTARY TRANSISTOR AND FORMING ELECTRICAL CONTACTS TO THE SOURCE, DRAIN AND GATE REGIONS OF BOTH DEVICCES.

Voltage reference and voltage level sensing circuit

Abstract: The sum of the threshold voltages of two transistors of different conductivity type is employed as a reference level in voltage sensing and other circuits A first transistor connected as a diode and its current source are connected in series between a pair of terminals to which a voltage to be sensed is applied A second transistor of different conductivity type than the first transistor is connected at its control electrode to the connection of the diode to its current source The conduction path of the second transistor in series with its load is connected at at least one end to one of the pair of terminals

Diffusion guarded metal-oxide-silicon field effect transistors

Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

Thin film electronic components on flexible metal substrates

Abstract: This disclosure is concerned with thin film field effect transistor (FET) formed on flexible metal substrates by vapor deposition techniques. The FET is electrically insulated from the metal substrate by an electrically insulating varnish.

Thermal feedback in power semiconductor devices

Abstract: Thermal feedback (TF) is an important aspect for the thermal management of semiconductor devices and high-power density integrated circuits. Different features of positive and negative TF in transistors are reviewed and summarized for the macroscopic domain. The thermal feedback mechanism is applied to the microscopic domain of noise fluctuations in semiconductor devices. It is argued that TF may be responsible for a major part of 1/ f flicker or excess noise. Some experimental evidence is presented which supports this thermal feedback 1/ f -noise theory for bipolar and MOS field effect transistors. Device and circuit design rules for the minimization of transmitter noise are given.

Predicted Effects of Neutron Irradiation on GaAs Junction Field Effect Transistors

Abstract: The fast-neutron-induced degradation of the properties of n-channel GaAs junction field effect transistors (JFET) is estimated and the results are compared with the effects produced in n-and p-channel silicon field effect transistors. The estimated degradation of the maximum transconductance, maximum drain current, pinch-off voltage, and cutoff frequency is based on electrical measurement data taken for fast-neutron-irradiated bulk n-type GaAs samples. It is concluded that n-channel GaAs JFET's should be at least as resistant to fast neutrons as either n-or p-channel Si JFET's.

Methods of manufacturing insulated gate field effect transistors

Abstract: A method of making an IGFET by implantation techniques is described. The method features provision of the source and drain contact metal on the semiconductor surface and an adjoining insulator, provision of a gate electrode structure which will mask ions, and then ion bombardment under such conditions that the ions do not penetrate the gate electrode structure thereby defining a channel precisely aligned with the gate, but ions do penetrate the adjacent structure to form in the underlying semiconductor source and drain surface regions wholly defined by the implantation and whose p-n junctions terminate under the insulator. Upon completion, the source and drain contacts for the source and drain regions are automatically established. Various methods are described for controlling the locations where the ions are masked or are permitted to penetrate into the semiconductor.