Showing papers on "Field-effect transistor published in 1975"

A hydrogen−sensitive MOS field−effect transistor

Abstract: An MOS transistor in silicon with 10−nm silicon dioxide as gate insulator and 10−nm palladium as gate electrode was fabricated. The threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C it was possible to detect 40 ppm hydrogen gas in air with response times less than 2 min.

Signal and Noise Properties of Gallium Arsenide Microwave Field-Effect-Transistors

Abstract: Publisher Summary This chapter examines the signal and noise properties of gallium arsenide (GaAs) microwave field-effect transistors (FET) High frequency gallium arsenide field-effect transistors (GaAs FETs) have demonstrated remarkably low noise figures and high power gains at microwave frequencies A practical microwave GaAs FET is usually fabricated by deposition or diffusion of source, gate, and drain contacts on the surface of an appropriately doped thin epitaxial n-type layer This layer, in turn, is grown on a semi-insulating wafer by either a vapor or liquid epitaxial technique The apparent minor role played by the negative resistance region in practical short-gate FETs suggests that radiofrequency instabilities due to this region, if they exist, occur at frequencies far above the normal frequency regime of microwave FETs The small-signal equivalent circuit of the FET, valid up to moderately high frequencies is elaborated It is found that noise in a microwave GaAs FET is produced both by sources intrinsic to the device and by thermal sources associated with the parasitic resistances

Field-effect transistor versus analog transistor (static induction transistor)

Abstract: The reason why the usual FET shows the saturated characteristics has been shown that with increasing drain voltage, the effect of the negative feedback action, increases through a marked increase of the Series channel resistance in the neighborhood of the pinch-off voltage, under which condition the apparent transfercon-ductance G_{m'}= G_{m}/(1 + r_{s}.G_{m}) becomes G_{m'} \simeq r_{s}^{-1} . It is also pointed out that a transistor in analogy to the vacuum type proposed by Watanabe and Nishizawa in 1950, exhibits the nonsaturated build-up character only When the internal negative feedback action is as little as G_{m'} \simeq G_{m} . In this case, when the channel has not yet pinched off, the characteristics are ohmic and then the transistor can operate as a good variable resistor; on the other hand, when the channel has already pinched, the transistor shows the build-up characteristics similar to those of a vacuum tube triode as a result of the static induction from the drain. The transistor similar to that of the vacuum tube triode type is named "Static Induction Transistor," because its output character is based on the static induction as well as input characteristics. The SIT has the exponential characteristics in contrast with the "Analog Transistor" which is expected by Shockley to follow the space-charge conduction law. The SIT has already been ascertained to have low noise, low distortion, and high-power capability, and its fabrication has been already realized in the form of a high-power transistor (2 kW, 8 MHz), a high-frequency transistor (a few watts, UHF), and a high-speed thyristor. Microwave transistors and very high-speed integrated circuits are being constructed, as well as variable resistors.

Potassium ion-sensitive field effect transistor

Abstract: The construction and theory of operation of a potassiumsensitive field effect transistor Is described, and Its performance is characterized both as a solid-state field-effect device and as an electrochemical sensor. The performance of this device is comparable with the correspondlng PVC-type ion selective electrodes. The transistor operates satisfactorliy in the presence of proteins and it has been used for determination of potassium ion concentration in blood serum. A new type of electrochemical sensor, an ion-sensitive field-effect transistor (ISFET), was introduced when Bergveld removed the metal gate from a metal oxide semiconductor field-effect transistor (MOSFET) and exposed the silicon oxide gate insulator to a measured solution (I). A similar approach was followed later by Matsuo and Wise (Z), and this new subject area has been recently reviewed by Zemel (3). In the broader sense of chemically sensitive field-effect transistors, one sensitive to molecular hydrogen has also been reported (4). The ISFET is a result of the integration of two technologies: ion-selective electrodes and solid state microelectronics. This development opens several new possibilities, such as miniaturization, development of multiprobes, all solidstate design and in situ signal processing. Because of its small size, it presents a difficult encapsulation and packaging problem which is, however, amply offset by the elimination of electrical pick-up noise by in situ impedance conversion and on site signal amplification. Bergveld did not modify the ion-sensitive layer in any way although he considered introducing impurities in order to render the device ion selective. In this paper, we introduce a class of devices having a chemically-sensitive layer placed over the gate region, and we report our results with valinomycin/plasticizer/poly(vinylchloride) membrane

The effect of randomness in the distribution of impurity atoms on FET thresholds

Abstract: Significant regions of the depletion layer of a field effect device may contain only hundreds of dopant atoms. The randomness of the distribution of impurity atoms means that the average doping in the depletion layer varies from place to place in the plane of the surface. The cube approximation introduced by Shockley is adopted and used to divide the channel region of an FET into cubes whose edge is equal to the thickness of the depletion layer. The probability distribution of the threshold voltages of the cubes can then be calculated by using the Poisson distribution of impurity numbers. The conductivity of the array of cubes is treated by a modification of percolation theory. The arrays of importance in the theory of the FET are not very large, containing only tens or hundreds of elements, and the differences between nominally identical arrays is of interest to the average behavior of a large system. Random number experiments are used to develop a quantitative description of the probability of conductivity thresholds in the two-dimensional site problem with a finite number of elements. The finite percolation theory is combined with the cube threshold probability distribution to yield the probability distribution of threshold voltages of a field effect transistor in equilibrium.

The effect of randomness in the distribution of impurity atoms on FET thresholds

Abstract: Significant regions of the depletion layer of a field effect device may contain only hundreds of dopant atoms. The randomness of the distribution of impurity atoms means that the average doping in the depletion layer varies from place to place in the plane of the surface. The cube approximation introduced by Shockley is adopted and used to divide the channel region of an FET into cubes whose edge is equal to the thickness of the depletion layer. The probability distribution of the threshold voltages of the cubes can then be calculated by using the Poisson distribution of impurity numbers. The conductivity of the array of cubes is treated by a modification of percolation theory. The arrays of importance in the theory of the FET are not very large, containing only tens or hundreds of elements, and the differences between nominally identical arrays is of interest to the average behavior of a large system. Random number experiments are used to develop a quantitative description of the probability of conductivity thresholds in the two-dimensional site problem with a finite number of elements. The finite percolation theory is combined with the cube threshold probability distribution to yield the probability distribution of threshold voltages of a field effect transistor in equilibrium.

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

Abstract: The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the I D -V D characteristics could be simulated by computer model based on the physical effects.

Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics

Abstract: A model of the effect of random fluctuations in the number of impurity atoms in the depletion layer of a field-effect transistor (FET) is presented and analyzed. It is conducted that the range of space charge per unit area that must be anticipated on a chip containing N FET's each of area A is /spl Delta/S=q(2 ln N)/SUP 1/2/A/SUP -1/4/n~/SUP 1/2/. n~ is the doping level of the substrate.

Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

Abstract: Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.

Semiconductor device and a method for fabricating the same

Abstract: A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.

Deep-channel MOS transistor

Abstract: A new type of ion-implanted MOS transistor is described. The transistor functions, for example, as an integrating nondestructively readable photosensor and its technology is fully compatible with the advanced MOS integrated circuits.

Through-substrate source contact for microwave fet

Abstract: A microwave field effect transistor (FET) comprises source, gate, and drain electrodes deposited on an epitaxial layer grown on a semi-insulating substrate. The FET has lowered thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxial layer. The chip, comprising the substrate, epitaxial layer, and top electrodes, is mounted on a heat sink. The chip's underside, including the bottom surface of the plated through source contact, is conductively bonded to the top surface of the heat sink.

Silicon on sapphire MOS transistor

Abstract: An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

Design and Performance of X-Band Oscillators with GaAs Schottky-Gate Field-Effect Transistors

Abstract: The circuit construction and design of an X-band oscillator with a GaAs Schottky-gate FET have been studied. The oscillation characteristics including stability and noise performance have been examined in order to clarify the position of a GaAs FET as a microwave solid-state oscillator device. The experiments have revealed that 1) the GaAs FET simultaneously possesses the most desirable features of both Gunn and IMPATT oscillators, i.e., low bias voltage operation and fairly high efficiency, and 2) it is situated between Gunn and GaAs IMPATT oscillators with respect to noise properties. The results indicate that the GaAs FET oscillator will soon be joining the family of microwave solid-state oscillators as a promising new member.

Design and performance of X-band oscillators with GaAs Schottky-gate field-effect transistors

Abstract: The circuit construction and design of an X-band oscillator with a GaAs Schottky-gate FET have been studied. The oscillation characteristics including stability and noise performance have been examined in order to clarify the position of a GaAs FET as a microwave solid-state oscillator device. The experiments have revealed that 1) the GaAs FET simultaneously possesses the most desirable features of both Gunn and IMPATT oscillators, i.e., low bias voltage operation and fairly high efficiency, and 2) it is situated between Gunn and GaAs IMPATT oscillators with respect to noise properties. The results indicate that the GaAs FET oscillator will soon be joining the family of microwave solid-state oscillators as a promising new member.

An experimental and theoretical analysis of double-diffused MOS transistors

Abstract: An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made. A simple, analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics. Both the model and experimental results show that three distinct regions of operation exist: short-channel control, long-channel control, and carrier velocity saturation control. Quantitative criteria are established for judging the region of operation as a function of device parameters and terminal voltages. A DMOST may be optimized to have the same d.c. characteristics as its short-channel component transistor over most of its operating range. A two-transistor model suitable for Computer-Aided Circuit Design (CAD) is also presented.

Electronic circuit using field effect transistor with compensation means

Abstract: A compensation circuit for electronic circuits such as pulse generator circuits which are suitable for MOSICS includes a resistor of high resistance and parallel-connected MOSFETs of the enhancement type and depletion type, respectively. The drain electrodes of the MOSFETs are connected to a power supply through the resistor, and are also connected to the gate electrode of load MOSFET of the depletion type which constitutes a load for a MOSFET of the enhancement type. To the gate of the former enhancement type MOSFET, a controlled bias voltage is applied from the connection point of MOSFETs connected in series between the power supply and ground. By employing the compensation circuit in pulse generator circuits, the instability of the oscillating periods due to changes in the ambient temperature and changes in the supply voltage is compensated. Also, the differences of oscillating periods are decreased among MOSICs.

Method and structure for controllng carrier lifetime in semiconductor devices

Abstract: The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

Method for manufacturing a semiconductor field effort transistor

Abstract: A method of manufacturing a metal, insulator, semiconductor type field effect transistor (MISFET) is disclosed by which a device is obtained having greatly improved reliability and containing multi-layered wiring. Only three photo-mask processes are used and the requirement for precision mask aligning is eliminated.

Self-aligned integrated circuits

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.

Transistor protection circuit

Abstract: The disclosed protection circuit which is suitable for providing protection of transistors included in integrated circuits such as regulators and power amplifiers, includes thermal shutdown, safe area and current control circuits. The current control portion includes a sense transistor connected substantially in parallel with the transistor to be protected. In monolithic integrated circuit applications, the sense transistor has an emitter area that is a predetermined ratio of the emitter area of the protected transistor. A "sense resistor" is connected to the sense transistor and develops a control signal which is proportional to the instantaneous current being conducted by the protected transistor. A threshold circuit is coupled between the sense resistor and the drive circuit for the protected transistor and responds to the magnitude of the control signal crossing a predetermined threshold to remove or reduce the drive to the protected transistor.

Semiconductor floating gate storage device with lateral electrode system

Abstract: A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.

Influence of the channel width on the threshold voltage modulation in m.o.s.f.e.t.s

Abstract: The threshold vollage of an m.o.s. field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.

Multiplication mode bistable field effect transistor and memory utilizing same

Abstract: A novel solid state device which exhibits two-terminal negative resistance characteristics. The negative resistance characteristic may be readily shaped by external bias control, providing a wide range of oscillatory or bistable properties. The negative resistance characteristic is obtained by a novel means of device operation exploiting an electron hole pair multiplication effect which is enhanced by high substrate doping in conjunction with appropriate biasing of the junctions within the device. The device exhibits a bias voltage controlled small signal negative resistance region, i.e., the device has a unique feature, a negative slope over an adjustable portion of its V-I characteristic. Bistable action is obtained with a single device. In the first stable state ("off") of the device, power dissipation is zero. In the second stable state ("on") of the device, power dissipation is adjustable to less than one micro-watt. One embodiment of the device is a novel and unobvious modification of a known N channel FET structure. The device may be readily fabricated by using large scale integration techniques well known in present day FET technology. The novel solid state device has utility in at least the following applications: (1) high density non-refresh memory; (2) gated latch (as three terminal device); (3) astable, monostable and bistable devices; (4) level detector, and (5) small signal (linear) oscillatory circuit.

Signal detector comprising field effect transistors

Abstract: A signal detector including a transducer element, an X-Y addressed array of field-effect transistor electrically coupled, e.g., capacitively or directly coupled, to the transducer element, and means for addressing the transistor X-Y array.

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

Abstract: The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage ( C - V ) characteristics of these devices. Techniques are presented for determining the impurity profile of the buried layer from the low frequency C - V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C - t ) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.

Field distribution in junction field-effect transistors at large drain voltages

Abstract: An analytical approximation to the field distribution in the channel portion between gate and drain of the junction field-effect transistor is derived, assuming an infinitely small channel width-to-height ratio, and modified for finite channel widths by introducing an effective impurity concentration which depends on drain current. The approximation is applicable also in the limiting case of zero gate edge curvature, i.e., for Schottky-barrier gate. The theoretical field distribution is used to extract impact-ionization coefficients from published experimental data on gate current enhancement at large drain voltages. These impact-ionization coefficients agree with published data derived from bulk impact ionization.

Frequency limits of GaAs and InP field-effect transistors

Abstract: Monte Carlo calculations of electron transport in InP and GaAs short-channel field-effect transisters (FET's) show that a significant departure from the equilibrium velocity-field curve occurs in these devices. On the basis of these calculations, InP FET's should have high-frequency performance superior to that of GaAs FET's only for effective channel lengths in excess of 1.5 µ.