Showing papers on "Field-effect transistor published in 1981"

Application of amorphous silicon field effect transistors in addressable liquid crystal display panels

Abstract: It is shown that thin-film field effect transistors (FETs) made from amorphous (a-) silicon deposited by the glow-discharge technique have considerable potential as switching elements in addressable liquid crystal display panels. The fabrication of the elements and their characteristics with steady and pulsed applied potentials are discussed in some detail. Two important points are stressed: (i) a-Si device arrays can be produced by well-established photolithographic techniques, and (ii) satisfactory operation at applied voltages below 15VV is possible. Small experimental 7×5 transistor panels have been investigated and it is shown that with the present design up to 250-way multiplexing could be achieved. The reproducibility of FET characteristics is good and in tests so far no change has been observed after more than 109 switching operations.

Fabrication process of sub-micrometer channel length MOSFETs

Abstract: Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

GaAs FET large-signal model and its application to circuit designs

Abstract: A large-signal GaAs FET model is derived based on dc characteristics of the device. Analytical expressions of modeled nonlinear elements are presented in a form convenient for circuit design. Power saturation and gain characteristics of a GaAs FET are studied theoretically and experimentally. An oscillator design employing the large-signal model is demonstrated.

Power-limiting breakdown effects in GaAs MESFET's

Abstract: State-of-the-art GaAs MESFET'S exhibit an output power saturation as the input power is increased Experiments indicated that this power saturation is due to the combined effects of forward gate conduction and reverse gate-to-drain breakdown This reverse breakdown was studied in detail by performing two-dimensional numerical simulations of planar and recessed-gate FET's These simulations demonstrated that the breakdown occurs at the drain-side edge of the gate The results of the numerical simulations suggested a model of the depletion layer configuration which could be solved analytically This model demonstrated that the breakdown voltage was inversely proportional to the product of the doping level and the active layer thickness

Amorphous silicon-silicon nitride thin-film transistors

Abstract: A thin‐film field‐effect transistor has been fabricated using glow‐discharge amorphous silicon as the semiconductor and silicon nitride as the insulator. The transistor operates in the electron (n type) accumulation mode and by changing the gate potential from zero to only 3 V a change in the source‐drain conductance of greater than four orders of magnitude is obtained. The results imply upper limits to the density of gap states in amorphous silicon and interface states at the amorphous silicon‐silicon nitride interface of 3×1016 cm−3 eV−1 and 5×1011 cm−2 eV−1, respectively.

Isolation for high density integrated circuits

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Electrically alterable double dense memory

Abstract: An electrically alterable double dense memory is provided which includes a field effect transistor having first and second spaced apart diffusion regions of a first conductivity defining a channel region at the surface of a semiconductor substrate having a second conductivity. First and second floating gates are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region. First and second dual charge injector structures or enhanced conduction insulators are disposed between the first and second floating gates and a common control gate of the transistor. A word line is connected to the control gate and first and second bit lines are connected to the first and second diffusion regions. By applying appropriate pulses to the word and bit lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region associated with the selected floating gate and then discharged at will. In this manner binary digits of information are stored in each of the two floating gates and altered as desired. By applying appropriate voltages to the control gate and to one of the first and second diffusion regions, the stored information or charge condition of the floating gate associated with the other of the first and second diffusion regions can be determined.

Ttl to cmos input buffer

Abstract: A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1" by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.

Overcurrent and overtemperature protective circuit for power transistor system

Abstract: A power transistor switch is protected against thermal destruction that might be caused by accidental short circuiting of the load being switched by a protective circuit having a base-drive-removing transistor in shunt to the base-emitter junction of the power transistor; an RC circuit including a capacitor in series with a resistor connected across the power transistor with the capacitor coupled across the base-emitter junction of the base-drive-removing transistor; a forward-biased shunting transistor connected across the capacitor; a shunt-removing transistor connected across the base-emitter junction of the shunting transistor; and a turn-on transistor triggerable to the conductive state by a turn-on signal for applying base drive to the power transistor and for forward biasing the shunt removing transistor to thereby turn off the shunting transistor and permit the capacitor to charge. Excessive current flow through the power switch causing it to desaturate results in charging the capacitor and consequent turning on the base-drive-removing transistor to thereby remove base current from the power transistor and turn it off.

An Active "Cold" Noise Source

Abstract: An active circuit which behaves like a "cold" noise source is described. The circuit which uses a gallium arsenide FET is given the name COLFET. The appropriate theory is developed and practical circuits described using the circuit. Equivalent noise temperatures of less than 50 K have been measured for a 50-omega source at 1400 MHz.

Depletion-mode FET for the regulation of the on-chip generated substrate bias voltage

Abstract: An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). The charge pump produces a substrate bias voltage (VBB) which is supplied to the gate of a depletion-mode field-effect transistor (28) whose source receives a reference voltage (VSS). The transistor forms part of a control circuit (14) coupled to the ring oscillator. In the N-channel case, the charge pumping action on the substrate drives the substrate bias negative until it reaches the sum of the reference voltage and threshold voltage of the depletion-mode transistor. This enables the control circuit to control the operation of the ring oscillator so as to regulate the substrate bias voltage.

Noise caused by GaAs mesfets in optical receivers

Abstract: In the application of GaAs metal-semiconductor field effect transistors (MESFETS) in ultra low-noise lightwave receivers, the channel noise is often the dominant effect in determining sensitivity. This paper analyzes for the first time the excess channel-noise factor Γ for GaAs by considering the effect of circuit capacitance, as well as gate-to-source capacitance on the correlation of gate and channel fluctuations, and derives a useful and analytic expression for Γ. For example, we find that Γ for practical GaAs MESFET amplifiers can be much larger than 1.1 as is usually assumed. The multiplication factor, Γ is approximately 1.75 for the practical GaAs MESFET with 1-μm gate length, which explains the discrepancy between the optical sensitivity from the noise calculation and experiments.

Solid state image pickup

Abstract: A Detection Matrix having elementary modules disposed in lines and in columns. Each module has a photoconductance, a thin-film MOS transistor and a storage capacitor. The gate of the transistor is connected to a line electrode. The source of the transistor is connected to a video amplifier, and the drain of the transistor is connected to one terminal of the photocapacitance and of the capacitor. The other terminal of the photoconductance of the capacitor are both connected to the line electrode following or preceding the line electrode connected to the gate of the transistor.

Measurement of GaAs field‐effect transistor electronic impulse response by picosecond optical electronics

Abstract: Direct time‐resolved measurements of the linear and nonlinear electronic impulse response of a high‐speed gallium arsenide metal semiconductor field‐effect transistor have been made by using picosecond optical pulses to drive high‐speed photoconducting electronic pulse generators and sampling gates. High resolution, jitter‐free measurements with excellent signal‐to‐noise showed the field‐effect transistor to have a fast full width at half‐maximum response of approximately 25 ps, and a slower fall time of 75 ps.

Saturation velocity determination for In0.53Ga0.47As field‐effect transistors

Abstract: The fabrication of Schottky‐gate field‐effect transistors (FET’s) on InGaAs lattice matched to InP is reported. A higher band‐gap interface layer is used to lower the gate leakage to acceptable levels. A technique to deduce the effective saturated electron drift velocity is given, which shows over a factor of 2 higher saturated velocity for InGaAs in comparison to GaAs when used as a FET material.

Self-aligned field effect transistor process

Abstract: A method for fabricating a semiconductor [integrated circuit] structure having a sub-micrometer gate length field effect transistor device is described. An isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistors [devices]. A heavily doped conductive layer and an insulator layer are formed thereover. The multilayer structure is etched to result in a patterned conductive layer having substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings in the pattern at the location of the field effect transistor channel. The pattern in the source/drain areas extend over the isolation pattern. A controlled sub-micrometer thickness insulating layer is formed on these vertical sidewalls. The sidewall insulating layer is utilized to controllably reduce the channel length of the field effect transistor. [The sidewall layer is preferably doped with conductive imparting impurities.] The gate dielectric is formed on the channel surface. The source/drain regions [and preferably lightly doped region] are [simultaneously] formed by thermal drive-in from the conductive layer [and sidewall insulating layer respectively]. The desired gate electrode is formed upon the gate dielectric and electrical connections made to the various elements of the field effect transistor devices. [The conductive layer and resulting contacts to said source/drain regions may be composed of polycrystalline silicon, metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.]

N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Abstract: Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.

Application of amorphous silicon field effect transistors in integrated circuits

Abstract: The work described in this paper is concerned with the possible applications in integrated circuits of thin-film field effect transistors (FETs) made from glow discharge amorphous (a-) silicon and silicon nitride. The construction and performance of inverter circuits, employing integrated a-Si load resistors, are described in some detail. The extension of this basic circuit to NAND and NOR gates, to a bistable multivibrator and to a shift register is reported. Based on the excellent photoconductive properties of a-Si an integrated addressable photosensing element has been constructed, which could have potential applications in imaging arrays.

Enhancement-mode high electron mobility transistors for logic applications

Abstract: Enhancement-mode high electron mobility transistors (E-HEMTs) with selectively doped GaAs/n-AlxGa1-xAs heterojunction structures grown by molecular beam epitaxy are described. E-HEMTs with 2- µm long gates have exhibited the square-law drain characteristic. The device has a gm of 409 mSmm-1 of gate width at 77 K and 193 mSmm-1 at 300 K. This value of gm at 77 K is the highest in all field effect devices reported thus far.

Electrically‐alterable read‐only‐memory using Si‐rich SiO2 injectors and a floating polycrystalline silicon storage layer

Abstract: Currently, electrically‐alterable read‐only‐memory (EAROM) has become increasingly important for memory and logic operations. A novel EAROM device in a field‐effect transistor (FET) configuration, which uses a floating polycrystalline silicon (poly‐Si) layer on top of thermal SiO2 and a dual electron injector structure (DEIS) between this floating poly‐Si and a control gate poly‐Si contact, is described. The DEIS stack consists of sequentially chemically vapor deposited (CVD) layers of Si‐rich SiO2 (46% atomic Si), SiO2, and Si‐rich SiO2 (46% atomic Si) between the poly‐Si layers. Electrons from either poly‐Si layer can move to the other poly‐Si layer biased at the higher voltage with moderate applied voltages. Thus, the floating poly‐Si storage layer can be charged with electrons (’’write’’ operation) or with positive charge (’’erase’’ operation) in milliseconds with negative and positive control gate voltages, respectively. The average electric fields in the intervening CVD SiO2 layer during writing and...

Growth of extremely uniform layers by rotating substrate holder with molecular beam epitaxy for applications to electro-optic and microwave devices

Abstract: Integrated optics and integrated microwave circuits require extremely uniform epitaxial layer thicknesses, composition profiles, and doping profiles. With a sample rotating mechanism, molecular beam epitaxy can for the first time prepare GaAs and AlxGa1−xAs layers with thickness variation of less than 1% over a lateral dimension of 5 cm. The variation of AlAs mole fraction of the Al0.3Ga0.7As over a 10‐cm2 area was less than 0.4%. The variation of the ’’pinch‐off’’ voltage for a field effect transistor structure was less than 1.4% over a 10‐cm2 wafer. These results represent the most uniform epitaxial layers ever prepared with any crystal growth technology.

Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

Abstract: A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Initial observations of optical injection locking of GaAs metal semiconductor field effect transistor oscillators

Abstract: An experiment is described in which the output of a GaAlAs laser, modulated at 2.345 GHz, was used to optically injection lock a GaAs metal semiconductor field effect transistor oscillator. A substantial reduction of the FM noise of the field effect transistor oscillator, associated with locking to the more stable modulation signal applied to the laser, was obtained. The locking range obtained was 5 MHz, but possibilities for considerably increasing this are suggested.

Charge pumping in SOS—MOS transistors

Abstract: The variation of the floating-substrate potential of SOS-MOS transistors is studied by applying frequent pulses to the gate. The minority carriers are injected into the floating substrate by charge pumping and they recombine there. The injected charges are stored because of the reverse-biased junctions at the source and drain. The threshold-voltage change by the substrate bias is also investigated. If the silicon film is fully depleted under the gate, the threshold-voltage change does not occur. This condition is used to stabilize the high-speed operations of the SOS-MOS integrated circuits. A new memory cell consisting of only one transistor without a storage capacitor is realized utilizing the change of the floating-substrate potential by the charge pumping and the avalanche multiplication. The sensitivity of the memory cell is affected by the channel length of an SOS-MOS transistor. The memory storage time is obtained as 300 µs.

A Large-Signal Model for the GaAs MESFET

Abstract: An analytic Iarge-signal model for the GaAs FET is described which relates the terminal currents to the instantaneous terminal voltages and their time derivatives. It incorporates the device geometry and semiconductor parameters as well as the device parasitic circuit elements. The model is fast and efficient when implemented on a computer and is in a form suitable for large-signal circuit design and optimization.

Semiconductor memory circuit with depletion data transfer transistor

Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.