Showing papers on "Field-effect transistor published in 1983"

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.

Electrical properties of polyacetylene/polysiloxane interface

Abstract: Polyacetylene/polysiloxane interface states have been investigated using metal‐insulator‐semiconductor (MIS) diodes. The 1‐mm2 MIS diodes (Al/polysiloxane/polyacetylene) have been fabricated by use of a conventional photolithographic technique. The I‐V and C‐V measurements were used to explore the polyacetylene/polysiloxane interface electrical properties. The electrical conduction mechanism in this interface was found to be a Schottky‐Richardson mechanism. Using the C‐V measurements to determine the interface states density distribution, it was found that the distribution had a U shape in the gap and its minimum value was 6×1013 eV−1 cm−2. An attempt was made to fabricate an insulating gate field‐effect transistor which worked as a depletion‐type transistor with a very low transconductance, gm =13 nΩ−1.

Numerical analysis of heterostructure semiconductor devices

Abstract: A numerical method for analyzing heterostructure semiconductor devices is described. The macroscopic semiconductor equations for materials with position-dependent dielectric constant, bandgap, and densities-of-states are first cast into a form identical to that commonly used to model heavily doped semiconductors. Fermi-Dirac statistics are also included within this simple, Boltzmann-like formulation. Because of the similarity in formulation to that employed for heavily doped semiconductors, well-developed numerical techniques can be directly applied to heterostructure simulation. A simple one-dimensional, finite difference solution is presented. The accuracy of the numerical method is assessed by comparing numerical results with special-case, analytical solutions. Finally, we apply numerical simulation to two heterostructure devices: the heterostructure bipolar transistor (HBT) and the modulation doped field-effect transistor. The influence of a conduction band spike on the current-voltage characteristics of the HBT emitter-base junction is studied, and the variation with gate bias of the two-dimensional electron gas in a field-effect device is also investigated.

The COMFET—A new high conductance MOS-gated device

Abstract: A new MOS gate-controlled power switch with a very low on-resistance is described The fabrication process is similar to that of an n-channel power MOSFET but employs an n--epitaxial layer grown on a p+substrate In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability

Optical Control of GaAs MESFET's

Abstract: Theoretical and experimental work for the performance of GaAs MESFET's under illumination from light of photon energy greater than the bandgap of the semiconductor is described. A simple model to estimate the effects of light on the dc and RF properties of MESFET'S is presented. Photoconductive and photovoltaic effects in the active channel and substrate are considered to predict the change in the dc equivalent circuit parameters of the FET, and from these the new Y- and S-parameters under illumination are calculated. Comparisons with the measured S-parameter's without and under illumination show very close agreement. Optical techniques can he used to control the gain of an FET amplifier and the frequency of an FET oscillator. Experimental results are presented showing that the gain of amplifiers can be varied up to around 20 dB and that the frequency of oscillators can be varied (tuning) around 10 percent when the optical absorbed power in the active region of the FET is varied by a few microwatts. When the laser beam is amplitude-modulated to a frequency close to the free-running FET oscillation frequency, optical injection locking can occur. An analytical expression to estimate the locking range is presented. This shows a fair agreement with the experiments. Some suggestions to improve the optical locking range are presented.

Current—Voltage and capacitance—Voltage characteristics of modulation-doped field-effect transistors

Abstract: A model describing I-V and C-V characteristics of modulation doped FET's is developed and used to predict the performance of Al x Ga 1-x As/GaAs FET's in good agreement with our experimental results. It is shown that the change in the Fermi energy with the gate voltage changes the effective separation between the gate and the two-dimensional electron gas by about 80 A. Current-voltage characteristics were calculated using a two piece as well as a three piece linear approximation for the electron velocity and compared with experimental results. At 300 K, the two piece model overestimates the current predicted by the three piece model only by approximately 10-20 percent. At 77 K, however, the three piece linear approximation for the velocity field characteristic should be used since the electron mobility decreases very abruptly at about 200 V/cm. The effect of the nonlinear source resistance is also discussed along with the gate-to-source and gate-to-drain capacitances, parameters of paramount importance in determining device performance. These capacitances are calculated as functions of gate-to-source and drain-to-source voltages below saturation.

Improving the Power-Added Efficiency of FET Amplifiers Operating with Varying-Envelope Signals

Abstract: A technique is proposed for improving the power-added efficiency of linear, class-A FET power amplifiers operating with varying-envelope signafs. It involves dynamically controlling the gate "dc" bias voltage with the envelope of the input RF signal. It is shown theoretically that this technique, which is referred to as "class A," results in a significant improvement in the power-added efficiency over standard class A, independently of the FET power gain. The efficiency is also better than that of standard class B if the FET gain is less than about 10 dB, which is the case normally encountered at higher microwave frequencies. The practical implementation of class /sup /spl equiv//A requires FET's with essentially linear drain-current-versus-gate-voltage transfer characteristics.

Direct observation of dislocation effects on threshold voltage of a GaAs field‐effect transistor

Abstract: The threshold voltage of a GaAs metal‐semiconductor field‐effect transistor (MESFET) fabricated on a liquid encapsulated Czochralski grown, semi‐insulating substrate was found to be influenced by growth‐induced dislocations. Field‐effect transistors located at less than 20–30 μm from a dislocation exhibited a threshold voltage lower than that of FET’s located far from a dislocation. The maximum difference in threshold voltage of FET’s located at less than and more than this critical distance was obtained to be about 300 mV. The first definitive correlation between dislocations and FET threshold voltage is reported.

Electron density of the two-dimensional electron gas in modulation doped layers

Abstract: The electron density of the two‐dimensional electron gas in modulation doped structures is calculated as a function of the doping density in (Al,Ga)As, the thickness of the undoped (Al,Ga)As layer, the lattice temperature, and other device parameters. The results of the calculation show that the depletion approximation is not accurate enough and that the Fermi–Dirac statistics (rather than the Boltzmann statistics) should be used in the calculation. A simple analytical model which takes these factors into account is shown to be in good agreement with our computer calculations and experimental data. The obtained results may be used to evaluate the maximum intrinsic transconductance and the maximum gate voltage swing for the modulation doped field effect transistors.

Novel real-space hot-electron transfer devices

Abstract: A new class of devices based on hot-electron transfer between two conducting layers is proposed. The essential feature of these devices is a pronounced negative differential resistance (NDR) in the drain circuit, controlled by gate and substrate voltages. This allows a novel type of bistable logic element, which, although being unipolar, is comparable to the CMOS inverter in that a significant current is drawn only during switching. Another possible application is a gate-controlled microwave generator and amplifier. In the present work, the above device concepts are analyzed in the instance of GaAs/ GaAlAs heterojunction realizations.

Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

Abstract: A complete set of processes sufficient for manufacture of n‐metal‐oxide‐semiconductor (n‐MOS) transistors by a laser‐induced direct‐write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n‐doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1‐μm and 1‐μm‐thick gate oxides were micromachined with and without etchant gas, and the exposed p‐Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser‐induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n‐MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser‐induced surface reactions that have not been reported previously.

Silicon-on-insulator bipolar transistors

Abstract: Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.

A voltage-controlled resistance with wide dynamic range and low distortion

Abstract: Field-effect transistors (FET) can be used as voltage-controlled resistors, provided operation in the saturation region is avoided. However, to keep distortion low, the magnitude of the drain-to-source voltage must be kept low. This is true even when drain-to-gate feedback is applied to linearize the drain-current versus drain-to-source voltage characteristics. It is shown here that by employing a dependent source and a FET, a voltage-controlled resistance can be realized which has a linear range considerably greater (an order of magnitude or more) than other FET voltage-controlled resistances. The resulting circuit is stable and easy to implement.

Multi-bit-per-cell read only memory circuit

Abstract: A data memory circuit is provided including a plurality of depletion type MOS transistors connected in series, each of which stores data including two bits in the form of a threshold voltage. One end of the memory circuit is kept at a power source level and the second terminal thereof is kept at a ground potential level. 0 V is applied to the gate electrode of one selected MOS transistor while the power source voltage is applied to the gate electrodes of the remaining MOS transistors. As a result, a voltage equal to an absolute value of the threshold voltage of the selected MOS transistor is produced at the second terminal. A converter converts the voltage produced at the second terminal into corresponding binary coded data.

Compact DC model of GaAs FETs for large-signal computer calculation

Abstract: A modified, simple and fairly accurate explicit expression of DC current-voltage characteristics of GaAs FETs is presented. A departure from the square-law behavior in saturation of the short channel transistor is included by introducing drain-source voltage bias dependent pinch-off potential. The model proposed here needs four parameters extracted by the global curve-fitting technique of a measured family of drain current-voltage characteristics. A comparison with other DC compact models of MESFETs valid over the entire range of drain-source voltages shows good compromise between simplicity and accuracy of the model proposed. The model can be easily implemented in programs of computer-aided analysis and design of circuits with GaAs FETs.

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

Abstract: This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.

High-Frequency Doubler Operation of GaAs Field-Effect Transistors

Abstract: A comprehensive study of single-gate GaAs FET frequency doublers is presented. Special emphasis is placed on exploring high-frequency limitations, while yielding explanations for previously observed lower frequency phenomena as well. Extensive Iarge-signal simulations demonstrate the underlying relationships between circuit performance characteristics and principal design parameter. Verifying experiments include straight frequency doubler and a self-oscillating doubler, both with output signal frequencies in Ku-band. The self-oscillating doubler appears especially attractive, yielding an overall dc-to-RF efficiency of 10 percent. The type of transistor employed in the numerical and experimental examples possesses a gate length of 0.5 µm and a gate width of 250 µm.

An As-P(n + -n - )double diffused drain MOSFET for VLSI's

Abstract: An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

The characteristics and properties of optimised amorphous silicon field effect transistors

Abstract: A series of experiments aimed at improving the performance of amorphous silicon field effect transistors has been carried out. The dc and dynamic characteristics of the optimised devices are described. Stable devices capable of ON-currents of the order of 100 μA with OFF-currents ≃10−11 A can be fabricated which could, in principle, be used to address more than 1000 lines of a liquid crystal display. The properties of the highly conducting ON-state channel have also been studied. The field effect mobility, 0.3 cm2 V−1 s−1 at room temperature, has an activation energy of 0.1 eV at the higher gate voltages. The possible reasons for the improvement in performance over earlier devices are discussed.

The effect of interfacial traps on the stability of insulated gate devices on InP

Abstract: Measurements of the change in channel current with time following application of a step voltage to the input of enhancement‐mode insulated gate Field‐Effect Transistors (FETs) on InP are reported. The data indicate that, following an initial steady‐state period, the current varies exponentially with inverse temperature and logarithmically with time. This behavior suggests that a thermally activated tunneling process is responsible for the drift in these structures but leaves unanswered the question of the origin of the states responsible. It does appear, however, that, whereas its complete removal may be counterproductive, the proper preparation of the native oxide layer beween the InP and the deposited dielectric may be determinative in the establishment of a low‐trap density interface.

Theoretical Analysis of Amorphous-Silicon Field-Effect-Transistors

Abstract: Static characteristics of amorphous-silicon field-effect transistors have been analyzed under the assumption that the localized state density distribution (LSDD) in amorphous-silicon with respect to energy takes on an exponential or uniform form. In the case of an exponential LSDD, logarithmic drain current ID vs logarithmic gate voltage VG characteristics of the FET for large VG is found to be linear, the slope of which yields the characteristic temperature of the exponential LSDD. While, in the case of a uniform LSDD, log (IDVG)–VG curves for large VG are found to be linear. The experimental data is qualitatively in good agreement with the theoretical results of the exponential LSDD.

Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits The method for forming integrated circuits with this structure includes forming openings in a first polycrystalline silicon layer overlying an insulator by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces The openings are in those areas designated to be the gate regions of the field effect transistors A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body The gate dielectric is formed hereat A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions A blanket layer of a plastic material is used to planarize the surface by reactive ion etching the plastic material and the conductive layer until the tops of the narrow dimensioned regions are reached The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less The source and drain electrodes are thusly formed

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO 2

Abstract: A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.

Microwave Characteristics of an Optically Controlled GaAs MESFET

Abstract: This paper presents the results of an experimental investigation of microwave characteristics of a GaAs MESFET under optically direct-controlled conditions. The gain, drain current, and S-parameters were measured under various optical conditions in the frequency region from 3.0 GHz to 8.0 GHz, and it was found that they can be controlled by varying the incident light intensity in the same manner as when varying the gate bias voltage. As applications of this phenomenon, optical/microwave transformers and an optically switched amplifier were investigated.

Method for manufacturing semiconductor Bi-CMOS device

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n+ -type buried layers therein, n-type wells are formed to extend to the n+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p+ -type external base region and p+ -type source and drain regions of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n+ -type collector contact region and n+ -type source and drain regions of the n-channel MOS transistor.

Series current limiter

Abstract: Field effect transistors are used in a series current limiter circuit. The field effect transistors are depletion type transistors and are interconnected in a manner to decrease conduction when an overvoltage or overcurrent condition is sensed. Biasing resistors are used to maintain the transistors in a non-conductive state until the overvoltage or overcurrent condition is removed.

Theory of hot electron emission from silicon into silicon dioxide

Abstract: We present Monte Carlo simulations of the hot electron emission from silicon into the oxide of metal oxide silicon transistors. The calculations include the pseudopotential band structure and quantum effects such as collision broadening due to the electron–phonon interaction. As a result, we present a set of transport parameters which well describes all hot electron effects in silicon (including saturation velocity and impact ionization). We also show that the collision broadening effect leads to an effective barrier lowering and may require that voltages be scaled down far below the interface barrier height of ∼3.1 V in order to avoid hot electron emission.

Method for fabricating complementary field effect transistor devices

Abstract: Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.

Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas

Abstract: A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.