Showing papers on "Field-effect transistor published in 1984"

High voltage semiconductor device

Abstract: A field effect transistor, a bipolar transistor, a PIN diode, a Schottky rectifier or other high voltage semiconductor device comprise a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction. The known use of a single high-resistivity body portion of one conductivity type to carry both the high voltage and to conduct current results in a series resistivity increasing approximately in proportion with the square of the breakdown voltage. This square-law relationship is avoided by the present invention in which a depleted body portion comprising an interleaved structure of first and second regions of alternating conductivity types carries the high voltage which occurs across the depleted body portion. The thickness and doping concentration of each of these first and second regions are such that when depleted the space charge per unit area formed in each of these regions is balanced at least to the extent that an electric field resulting from any imbalance is less than the critical field strength at which avalanche breakdown would occur in the body portion. The first regions in at least one mode of operation of the device provide electrically parallel current paths extending through the body portion.

Physics of amorphous silicon based alloy field‐effect transistors

Abstract: In this paper we develop a new theory to describe the characteristics of amorphous silicon based alloy field‐effect transistors. We show that the transition from below to above threshold operation occurs when the Fermi level in the accumulation region moves from the deep to tail localized states in the energy gap. The current‐voltage and capacitance‐voltage characteristics are related to the basic material parameters such as the distribution of localized states in the energy gap, band mobility, device geometry, channel doping, and series resistances. Our analysis shows that an on current in excess of 2×10−7 A/μm gate width can be obtained with a 10‐μm gate length. We also demonstrate that even in the above threshold regime the field‐effect mobility is dependent on the gate voltage. Our theory can be used to optimize the design of amorphous silicon based alloy field‐effect transistors.

Lucky-electron model of channel hot-electron injection in MOSFET'S

Abstract: The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

Abstract: The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

The effect of high fields on MOS device and circuit performance

Abstract: A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

Abstract: A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.

Modulation-doped GaAs/AlGaAs heterojunction field-effect transistors (MODFET's), ultrahigh-speed device for supercomputers

Abstract: In the past few years, a new transistor has appeared on the scene, made of GaAs and AlGaAs, which now holds the record as the fastest logic switching device, switching at speeds of close to ten trillionths of a second (10 ps). The device evolved from the work on GaAs-AlGaAs superlattices (thin alternating layers of differing materials sharing the same crystalline lattice) pioneered by L. Esaki and R. Tsu at IBM in the late 1960's. They realized that high mobilities in GaAs could be achieved if electrons were transferred from the doped and wider band-gap AlGaAs to an adjacent undoped GaAs layer, a process now called modulation doping. R. Dingle, H. L. Stormer, A. C. Gossard, and W. Wiegmann of AT&T Bell Labs, working independently, were the first to demonstrate high mobilities obtained by modulation doping in 1978, in a GaAs-AlGaAs superlattice. Realizing that such a structure could form the basis for a high-performance field-effect transistor (Bell Labs Patent 4163237, filed on April 24, 1978), researchers at various labs in the United States (Bell Labs, University of illinois, and Rockwell), Japan (Fujitsu), and France (Thomson CSF) began working on this device. In 1980, the first such device with a reasonable microwave performance was fabricated by the University of Illinois and Rockwell, which they called a modulation-doped FET or MODFET. The same year Fujitsu reported the results obtained in a device with a 400-µm gate which they called the "high electron mobility transistor" or HEMT, in the open literature. Thomson CSF published shortly thereafter calling their realization a "two-dimensional electron gas FET" or TEGFET, and Bell Labs followed, using the name "selectively doped heterojunction transistor" or SDHT. These names are all descriptive of various aspects of the device operation as we will discuss in the text. For the sake of internal consistency will call it MODFET, hereafter. In this paper we review the principals of MODFET operation, factors affecting its performance, optimization of the device, and comparison with other high-performance compound and elemental semiconductor devices. Finally, the remaining problems and future challenges are pointed out.

Structure-enhanced MOSFET degradation due to hot-electron injection

Abstract: Device degradation due to channel hot-electron injection in several nonconventional MOSFET structures including minimum-overlap gate, offset gate, graded drain, and lightly doped drain (LDD) structures are evaluated. In these nonconventional structures the device degradation is much faster than that in conventional devices when biased with the same amount of hot electrons in the channel. This faster degradation rate is proposed to be due to external channel pinchoff at the more lightly doped drain edge. This behavior implies even more severe constraints on the operating regime for these nonconventional device structures at submicrometer gatelengths to maintain adequate reliability margins.

A Simple Model for Separating Interface and Oxide Charge Effects in MOS Device Characteristics

Abstract: A simple model to describe radiation effects on MOSFET electrical characteristics is presented. The key assumption is that mobility degradation in an enhancement mode MOSFET is predominantly due to charged interface traps. Model predictions are compared with measured values of interface trap density and device I - V curves.

Subbands and charge control in a two-dimensional electron gas field-effect transistor

Abstract: A calculation of the subband structure and charge distribution in an AlxGa1−xAs/GaAs heterojunction as a function of gate voltage at room temperature has been performed. The results show that usually about 80% of the electrons in the channel are in the lowest two subbands and describe for the first time quantitatively the transition from the simple capacitive charge control regime to the regime where the channel density is no longer controlled by the gate voltage.

Thin film field effect transistor

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

A GaAs gate heterojunction FET

Abstract: A new semiconductor-insulator-semiconductor field-effect transistor has been fabricated. The device consists of a heavily doped n-type GaAs gate with undoped (Al,Ga)As as the gate insulator, on an undoped GaAs layer. This structure gives the device a natural threshold voltage near zero, well suited for low-voltage logic. The threshold voltage is, to first order, independent of Al mole fraction and thickness of the (Al,Ga)As layer. The layers were grown by MBE and devices fabricated using a self-aligned technique involving ion-implantation and rapid thermal annealing. A transconductance of 240 mS/mm and a field-effect mobility of about 100 000 cm2/V-s were achieved at 77 K.

Charge injection transistor based on real-space hot-electron transfer

Abstract: We describe a new transistor based on hot-electron transfer between two conducting layers separated by a potential barrier. The mechanism of its operation consists of controlling charge injection over the barrier by modulating the electron temperature in one of the layers. This physical principle is different from those employed in all previous three-terminal amplifying devices-which are based either on the modulation of a potential barrier (vacuum triode, bipolar transistor, various analog transistors) or on the modulation of charge in a resistive channel (field effect transistors). In contrast to this, the present device can be compared to a hypothetical vacuum diode whose cathode has an effective electron temperature which is controlled without inertia by an input electrode ("cathode heater"). The device has been implemented in an AlGaAs/GaAs heterojunction structure. One of the conducting layers is realized as an FET channel, the other as a heavily doped GaAs substrate. The layers are separated by an Al x Ga 1 - x As graded barrier. Application of a source-to-drain field leads to a heating of channel electrons and charge injection into the substrate. The substrate thus serves as an anode and the FET channel represents a hot-electron cathode, whose effective temperature is controlled by the source-to-drain field. Operation of the charge injection transistor is studied at 300, 77, and 4.2 K. At 77 K the existence of power gain is demonstrated experimentally with the measured value of the mutual conductance g m reaching 280 mS/mm (at 300 K, g m ≈ 88 mS/mm). The fundamental limit on the device speed of operation is analyzed and shown to be determined by the time of flight of electrons across a high-field region of spatial extent ∼ 10-5cm. Practical ways of approaching this limit are discussed. The process of hot-electron injection from the channel is studied experimentally at 77 and 4.2 K with the purpose of measuring the electron temperature in the channel at different bias conditions. For not too high substrate bias the electron temperature in the channel is found to be proportional to the square of the heating voltage.

Piezoelectric effects in GaAs FET's and their role in orientation-dependent device characteristics

Abstract: Elastic stresses are frequently induced in GaAs substrates during the fabrication of FET's, particulariy in the vicinity of windows in dielectric overlayers. It is shown here that these stresses can produce piezoelectric charge densities of such magnitude to appreciably shift the pinchoff voltage and saturation current of FET's. These shifts are of opposite sign for FET's oriented along [011] and [011] directions on

Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film

Abstract: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film and the surface of the metal silicide film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no short-circuiting is necessary. For example, in an insulated gate field effect transistor, the gate electrode is constituted by the polycrystalline silicon layer and the metal silicide film at the side walls of the polycrystalline silicon layer. Such a gate electrode has a low electrical resistance and does not cause undesirable short-circuiting with source and drain regions by the existence of the silicon oxide film formed on the surface of the metal silicide film. Also, other metal silicide film may be formed on the upper surface of the gate electrode. Moreover the silicide-SiO 2 structure may be used on the source and drain regions.

Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics

Abstract: A procedure has been developed for producing accurate and unique small-signal equivalent circuit models for carrier-mounted GaAs FET's. The procedure utilizes zero drain-source bias S parmeter tests to determine accurate values of carrier parasitics, and dc measurements to evaluate the FET's gate, source, and drain resistances. Subsequent S-parameter measurements at full bias are then used to resolve the FET into an equivalent circuit model that has only 8 unknown elements out of a possible 16. A technique for evaluating the frequency range of accurate data is presented and the FET model shown is useful well above the maximum frequency of measurement. Examples of device diagnostics are presented for RCA flip-chip mounted GaAs FET's.

Metal‐semiconductor field‐effect transistors fabricated in GaAs layers grown directly on Si substrates by molecular beam epitaxy

Abstract: Device‐quality GaAs layers have been grown directly on Si(100) substrates by molecular beam epitaxy. Metal‐semiconductor field‐effect transistors have been fabricated in these layers with transconductance as high as 85 mS/mm and leakage current as low as 1 μA at Vgs =−3 V for gate dimensions of 2.0 μm×200 μm.

A novel wide dynamic range silicon photodetector and linear imaging array

Abstract: A silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed. This photodetector, which can be integrated on the same chip with MOSFET circuits or CCDs, provides an analog voltage signal over a wide dynamic range. Photodetector and arrays showed, in the visible spectrum an incoming radiation-detection light-intensity dynamic range of greater than 10/SUP 7/. In addition, the photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. The theory of the new photodetector device and its use in forming linear imaging arrays are discussed. Experimental results are presented.

Inversion-mode insulated-gate gallium arsenide field-effect transistors

Abstract: Inversion-mode insulated field-effect transistor structures are provided wherein a lightly-doped GaAs drift or drain region is combined with a gate-controlled channel structure comprising a film or layer of a semiconductor layer other than GaAs and within which inversion regions may more readily be formed. Suitable semiconductor materials for the gate-controlled channel structure are InP and Ga x In 1-x As. Presently preferred is a Ga x In 1-x As graded layer wherein x ranges from 1.0 to about 0.47.

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

Abstract: A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.

Integrated circuit high voltage protection

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

The hemt: A superfast transistor: An experimental GaAs-AlGoAs device switches in picoseconds and generates little heat. This is just what supercomputers need

Abstract: A description is given of an experimental GaAs-AlGaAs device that switches in picoseconds and generates little heat. Known as MODFET or HEMT, the device is compared to other less conventional devices, and an outline is presented of its operation.

Parasitic MESFET in (Al, Ga) As/GaAs modulation doped FET's and MODFET characterization

Abstract: A charge-control model for n-channel modulation doped FET's (MODFET's) is extended to include the drain-to-source current through the doped (Al, Ga)As layer which becomes important for large positive gate voltages. This parasitic conduction leads to decreased device transconductances at high gate voltages. A unified and complete characterization technique for deducing the parameters of our model is introduced and used for the device characterization. Parameters, e.g., the saturation velocity, two-dimensional gas concentration at equilibrium, thickness of the doped (Al, Ga)As layer, etc., deduced using the model, are in good agreement with the independent calculations and measurements. However, the deduced values of the room-temperature low field mobility of the two-dimensional electron gas are considerably smaller than those measured by Hall effect and in long-gate MODFET's. This model is in good agreement with the characteristics of high-current normally on MODFET's. The maximum measured current swing of 300 mA/mm gate is reported.

Lateral resurfed COMFET

Abstract: A lateral resurfed COMFET structure is proposed. The conductivity of the drift region of the device is modulated as in the case of vertical COMFET. However, the maximum operating current and switching speed are expected to be several times that of the vertical structure because of the collection of excess minority carriers by the p?-substrate and the narrow width of the n? epitaxial layer.

Mosfet and MOS Capacitor Responses to Ionizing Radiation

Abstract: The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of "slow" states can interfere with the interface-state measurements.

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

Abstract: The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

Fabrication of metal‐epitaxial insulator‐semiconductor field‐effect transistors using molecular beam epitaxy of CaF2 on Si

Abstract: Fabrication of metal‐epitaxial insulator‐semiconductor field‐effect transistors by molecular beam epitaxial growth of CaF2 on Si is reported for the first time. These devices have a room‐temperature electron mobility of 300 cm2/Vs and a threshold voltage of 0.5 V. The breakdown voltage of the films ranges from ≳105 to ≳106 V/cm in different regions of the film. These devices will be important for the characterization and improvement of the interface transport properties of the CaF2/Si system.

Fabrication of GaAs MESFET Ring Oscillator on MOCVD Grown GaAs/Si(100) Substrate

Abstract: GaAs MESFET ring oscillators were successfully fabricated on silicon substrate. GaAs epitaxial layers were grown directly by MOCVD on Si(100) substrate. A typical transconductance of 200 mS/mm was observed for the FET of 1.0 µm × 10 µm gate. A minimum propagation delay time of 51 ps/gate at a power dissipation of 1.1 mW/gate was observed for an E/D gate ring oscillator with gate length of 1.0 µm.

Method of making vertical channel field controlled device employing a recessed gate structure

Abstract: A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.