Showing papers on "Field-effect transistor published in 1990"

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

Abstract: An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe. >

Broad-band determination of the FET small-signal equivalent circuit

Abstract: A method to determine the broadband small-signal equivalent circuit of field-effect transistors (FETs) is proposed. This method is based on an analytic solution of the equations for the Y parameters of the intrinsic device and allows direct determination of the circuit elements at any specific frequency or averaged over a frequency range. The validity of the equivalent circuit can be verified by showing the frequency independence of each element. The method can be used for the whole range of measurement frequencies and can be applied to devices exhibiting severe low-frequency effects. >

The oligothiophene‐based field‐effect transistor: How it works and how to improve it

Abstract: Metal‐insulator‐semiconductor field‐effect transistors (MISFETs) based on organic semiconductors, mainly conjugated organic polymers and oligomers, have been reported recently. Unlike conventional MISFETs, these devices work through the modulation of an accumulation layer at the semiconductor‐insulator interface. A model for organic MISFETs, derived by changing the classical equations according to this particular operating mode is proposed. The ohmic current, parallel to the channel current, and due to the nonrectifying character of source and drain contacts, has also been taken into account. According to this model, the characteristics of these organic devices can be improved by decreasing the doping level and the thickness of the semiconducting layer. Simple rules are deduced and applied to devices based on α‐conjugated sexithienyl.

In‐plane‐gated quantum wire transistor fabricated with directly written focused ion beams

Abstract: A new unipolar electronic device with a quasi‐one‐dimensional (1D) tunable carrier channel defined by directly written focused ion beams has been fabricated and characterized. Special features of the device are simple and rapid fabrication in one single technology step, inherent self‐alignment, and linear instead of planar gates with very low capacitances. High integration as well as ultrahigh speed operation in logical and linear applications are feasible. The striking new aspect of this in‐plane‐gate structure is that the confining electric field is parallel to the two‐dimensional electron gas, and the distorted, insulating region serves as a dielectric. Ballistic 1D transport is observed at low temperatures, and field‐effect transistor operation of the device is demonstrated up to room temperature.

Temperature dependence of threshold voltage in thin-film SOI MOSFETs

Abstract: A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime. >

Method of fabricating an high-performance insulated-gate field-effect transistor

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Complementary field effect transistors having strained superlattice structure

Abstract: The carrier mobilities for both electrons and holes in complementary field effect transistor structures such as CMOS and CMOD devices are increased by using strained Ge x Si 1-x /Si layers for the carrier conduction channels. The carrier mobilities for the holes and electrons can be of substantially the same magnitude which is advantageous for complementary logic applications. The complementary FET structures can be advantageously employed with bipolar devices in integrated circuits.

Monte Carlo analysis of semiconductor devices: the DAMOCLES program

Abstract: The behavior of small semiconductor devices is simulated using an advanced Monte Carlo carrier transport model. The model improves upon the state of the art by including the full band structure of the semiconductor, by using scattering rates computed consistently with the band structure, and by accounting for both long- and short-range interactions between carriers. It is sufficiently flexible to describe both unipolar and bipolar device operation, for a variety of semiconductor materials and device structures. Various results obtained with the associated DAMOCLES program for n- and p-channel Si MOSFETs, GaAs MESFETs, and Si bipolar junction transistors are presented.

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

Abstract: A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics. >

Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs

Abstract: A model developed to explain conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs is discussed. It is found that, unlike that which occurs in thin-film fully depleted n-channel devices, there is little or no coupling between the front and back gates, unless the surface-state density is so high that the film remains depleted even when an accumulation channel is formed. The apparent front threshold shift is explained by back-gate modulation of a body current, flowing from the source to the drain. Indeed, the body of the device presents a p/sup +/-p/sup -/-p/sup +/ structure whose conductivity is controlled by the depth of the depletion zones arising from the top and the bottom of the silicon film. The model is used to calculate drain current as a function of front- and back-gate bias as well as output characteristics. >

The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures

Abstract: A phenomenon called the MCCM (multistable charge-controlled memory) effect is observed in SOI MOS transistors working at lot temperatures. This MCCM effect essentially results in a controllable setting of the transistor threshold voltage by applying adequate voltage pulses (or up-down voltage sweeps) to one or more electrodes of the structure. A change in threshold voltage of several volts can be obtained. Stability on the order of hours and longer, depending on temperature and operational conditions, is observed. The physics behind the MCCM effect is discussed, and a simple analytical model is proposed. Some new applications based on the MCCM effect are briefly highlighted. >

Improved breakdown voltage in GaAs MESFETs utilizing surface layers of GaAs grown at a low temperature by MBE

Abstract: A metal-semiconductor field-effect transistor (MESFET) utilizing surface layers of GaAs grown at a low temperature by MBE (LT GaAs) under the gate electrode has been fabricated. The high trap density of LT GaAs reduces the surface fields of the FET, suppresses gate leakage, and increases the gate-drain breakdown voltage without sacrificing current drive capability. An undoped AlAs layer is incorporated between the LT GaAs layer and the channel as a barrier to the diffusion of excess As from the LT GaAs layer to the channel. A 74- mu m-gate-width device demonstrated an improved breakdown voltage of 34.85 V with a g/sub m/ of 144 mS/mm and an I/sub dss/ of 248 mA/mm. >

Interface circuits including driver circuits with switching noise reduction

Abstract: An interface circuit includes a generator for driving an interface signal to a receiver which produces an output signal in response thereto. The generator (or driver) includes a pair of relatively larger complementary conductivity field effect transistors and a pair of relatively smaller complementary conductivity field effect transistors (FETs), each pair in series circuit between the supply rails. The interface signal is produced at a connection of the center points of both pairs of FETs. A control device renders like ones of the FETs in each pair alternately conductive responsive to the input signal, however, the control device generates control signals for the FETs such that the relatively smaller FET of a given conductivity becomes conductive before the larger FET of that same conductivity. The receiver includes a voltage divider to attenuating and coupling the received interface signal to a high-gain amplifier which produces the output signal. Preferably, the signals have amplitudes sufficiently large to cause the interface circuit to operate as a digital interface. Further, it is preferred that two generators of opposite signal sense be employed to produce a differential interface signal, in which case the receiver includes a differential amplifier having opposite signal sense inputs to which the differential signals are applied through a differential voltage divider. In the preferred differential amplifier, opposite signal sense outputs are fed back in the regenerative sense to the two inputs to introduce hysteresis.

Determination of interface trap capture cross sections using three-level charge pumping

Abstract: A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO/sub 2/ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I/sub cp/ to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET.

Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs

Abstract: Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models. >

Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs

Abstract: The channel field and substrate current models developed for n-MOSFETs are applicable to p-MOSFETs. The impact ionization rate extracted for holes is found to be 8*10/sup 6/ exp (-3.7*10/sup 6//E), where E is the electric field. The lucky electron approach was used to model the gate current of surface-channel (SC) p-MOSFETs successfully. Device degradation in p-MOSFETs is due to trapped electrons in the oxide. p-MOSFET lifetime has good correlation with gate current in SC p-MOSFETs. The correlation is better than with substrate current. I/sub G/ can be larger in a buried-channel (BC) p-MOSFET than in a comparable SC n-MOSFET. This makes the SC MOSFET a much more reliable device. Device lifetime of a p-MOSFET under pulse stress can be predicted from DC stress data for inverterlike waveforms. For other waveforms, there is an extra degradation probably caused by the excess hot carriers generated during the gate turn-off transient. >

Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60-300 K

Abstract: Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q/sub b/, and inversion layer charge Q/sub i/. The experimental data for Q/sub b/ and Q/sub i/ were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) mu (E/sub eff/) dependence, which becomes more pronounced at low temperatures and low E/sub eff/, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures. >

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

Abstract: The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I/sub d/-V/sub g/ characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping. >

Effect of radiation-induced charge on 1/f noise in MOS devices

Abstract: The 1/f noise in MOS transistors is measured as a function of gate and drain bias, total ionizing dose, and postirradiation biased annealing time. The transistors tested varied in size, radiation hardness, and process technology. The radiation-induced 1/f noise correlates strikingly with the oxide trap charge through irradiation and anneal, but not with interface-trap charge, for frequencies up to 10 kHz. This implies that oxide trapped charge is the predominant factor which leads to the increased 1/f noise in irradiated MOS devices. >

Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs

Abstract: The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs. >

Esd protection for soi circuit

Abstract: PURPOSE: To make a protective circuit decreasing the thermal dissipation requirements of a thin semiconductor layer in SOI structure making feasible of the easy manufacture and the compatibility with another transistor on a chip by a method wherein a semiconductor body specifying a conductive channel between a semiconductor drain and a semiconductor source is provided with a FET formed of an SOI structure CONSTITUTION: An electrostatic discharge(ESD) protective device for SOI circuit is composed of an SOI structure containing a semiconductor material 20 conforming to the formation of a transistor therein, a conductor transmitting the signals relating to this transistor circuit and a field effect transistor 14 connected to this conductor conducting an ESD current and provided with a semiconductor body specifying a conductive channel 26 between a semiconductor drain 24 and source 22 while the semiconductor body contains the FET 14 formed of the SOI structure For example, the bulk material 26 in the conductive channel of the FET 14 is electrically separated from the residual semiconductor material 20 while a contact for connecting to the source region 22 is provided on a gateconductor 30

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Abstract: Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L/sub eff/=0.15 mu m and T/sub ox/=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO/sub 2/ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 mu m) and oxide thicknesses. >

Experimental confirmation of a new semiconductor detector principle

Abstract: A new detector-amplification principle proposed by Kemmer and Lutz in 1986 has been experimentally verified. Outstanding features of this device are the built-in amplification, the signal charge storage capability and the possibility of repeated non-destructive readout. The device was used for detection of X-rays from a 241 Am and from Am and from an 55 Fe source. Very low noise figures ( σ =30 electrons corresponding to an energy resolution of FWHM = 250 eV at 6 keV energy) have been obtained at room temperature. Various applications of the structure either as detector or as purely electronic element are possible. One of the most intriguing is the use as a pixel detector with random access non-destructive readout. This device may be operated at very low power, as only reading (of one single pixel at a time), not storing, consumes power. Further options of the device are fast clearing, gating and variation of the pixel size during readout. The latter property can be used to drastically increase the readout speed compared to more standard two dimensional devices as e.g. CCD detectors, as one may restrict the high density readout to regions of interest determined beforehand by a coarse scan of the whole detector. An alternative use of the device is as an analog or digital memory, or as a simple transistor with drastically reduced parasitic capacitances. Possible further developments are the combination with a novel three dimensional analog storage device which may either be used as a detector with built-in storage of several charge images or as a three dimensional analog memory.

Subthreshold CMOS amplifier with wide input voltage range

Abstract: A first linear voltage to current converter includes an MOS current source transistor with its gate connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A second linear voltage to current converter includes a bipolar current source transistor with its base connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A differential pair includes in each leg a bipolar current source transistor with its base connected to a source of fixed voltage feeding the source of an MOS follower transistor. A differential amplifer includes two circuit legs including these transistor circuits.

Multi-element-amorphous-silicon-detector-array for real-time imaging and dosimetry of megavoltage photons and diagnostic x-rays

Abstract: A multi-element-amorphous-silicon detector-array real-time imager and dosimeter for diagnostic or megavoltage X rays having megavoltage photons having a plurality of photodiodes (30) made of hydrogenated amorphous silicon arrayed in columns and rows upon a glass substrate (12). Each photodiode (30) is connected to a thin film field effect transistor (52) also located up-on the glass substrate (12). Upper and lower metal contacts (22, 38) are located below and above the photodiodes (30) to provide the photodiodes (30) with a reverse bias. The capacitance of each photodiode (30) when multiplied by the resistance of the field effect transistor (52) to which it is connected yields an RC time constant sufficiently small to allow real time imaging.

Unified charge control model and subthreshold current in heterostructure field-effect transistors

Abstract: A unified analytical charge control model covering the entire range of gate voltages from below and above threshold is developed for heterojunction field-effect transistors (HFETs). This model is based on a new interpretation of the quantized energy levels for the two-dimensional electron gas. It reduces to a classical charge sheet model in the limit of low surface field. The model is used to interpret the experimental data for the subthreshold regime of HFETs. The results indicate wide range variation of the effective acceptor concentration after device fabrication processing in the unintentionally doped GaAs buffer layer. >

Characterization of carrier generation in enhancement-mode SOI MOSFET's

Abstract: The carrier generation in enhancement-mode SOI MOSFETs is studied by applying a suitable bias step on one gate, which drives it from depletion of accumulation to stronger accumulation and creates a deep-depletion condition under the other gate. An accurate analysis of this technique is made through a critical reexamination of the physical mechanisms and assumptions involved. By carefully considering all the essential events taking place in the device as it relaxes back to steady state, a Zerbst-type expression is obtained for the resulting current transients, which leads to a straightforward evaluation of the generation lifetime and surface generation velocity. The method is used to study SIMOX transistors, and it is shown that a very long lifetime can be achieved by multiple oxygen implants. >

The influence of the measurement setup on enhanced AC hot carrier degradation of MOSFETs

Abstract: It is shown that the enhanced degradation and substrate current component, which is observed in several AC experiments at the falling edge of the gate pulse under high drain bias, can in some cases be primarily ascribed to a carrier injection due to the forward biasing of the source diode and a simultaneous drain voltage overshoot. The forward biasing of the source diode is not caused by the commonly known latch-up effect, which is triggered by the substrate current, but by an insufficient AC coupling of the source to the ground due to the parasitic inductance of the wiring. It is demonstrated that by putting a capacitor at the drain side of the transistor and grounding the source at the probe tip, the observed enhanced substrate current can be eliminated and the anomalous enhanced degradation reduced accordingly. >

One‐dimensional lateral‐field‐effect transistor with trench gate‐channel insulation

Abstract: A novel unipolar transistor device has been realized starting from two‐dimensional electron systems (2DES) in modulation‐doped AlGaAs/GaAs heterostructures. A 600‐nm‐wide 1D channel is insulated laterally from 2DES regimes by 700‐nm‐wide deep mesa etched trenches. The conductivity in the quasi‐one‐dimensional channel can be tuned via the in‐plane lateral field effect of the adjacent 2DES gates where the vacuum (or air) in the etched trenches serves as the dielectric. Room‐temperature operation is demonstrated yielding a 17 μS transconductance corresponding to 170 mS/mm 2D transconductance.