Showing papers on "Field-effect transistor published in 1993"

Shallow water analogy for a ballistic field effect transistor: New mechanism of plasma wave generation by dc current.

Abstract: We demonstrate that electrons in a ballistic field effect transistor behave as a fluid similar to shallow water. Phenomena similar to wave and soliton propagation, hydraulic jump, and others should take place in this electron fluid. We show that a relatively slow electron flow should be unstable because of plasma wave amplification due to the reflection from the device boundaries. This provides a new mechanism for the generation of tunable far infrared electromagnetic radiation.

High electron mobility transistor based on a GaN‐AlxGa1−xN heterojunction

Abstract: In this letter we report the fabrication and dc characterization of a high electron mobility transistor (HEMT) based on a n‐GaN‐Al0.14Ga0.86N heterojunction. The conduction in our low pressure metalorganic chemical vapor deposited heterostructure is dominated by two‐dimensional electron gas at the heterostructure interface. HEMT devices were fabricated on ion‐implant isolated mesas using Ti/Au for the source drain ohmic and TiW for the gate Schottky. For a device with a 4 μm gate length (10 μm channel opening, i.e., source‐drain separation), a transconductance of 28 mS/mm at 300 K and 46 mS/mm at 77 K was obtained at +0.5 V gate bias. Complete pinchoff was observed for a −6 V gate bias.

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Threshold voltage model for deep-submicrometer MOSFETs

Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

Bias‐stress‐induced stretched‐exponential time dependence of charge injection and trapping in amorphous thin‐film transistors

Abstract: The threshold voltage instabilities in nitride/oxide dual gate dielectric hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors are investigated as a function of stress time, stress temperature, and stress bias. The obtained results are explained with a multiple trapping model rather than weak bond breaking model. In our model, the injected carriers from the a‐Si:H channel first thermalize in a broad distribution of localized band‐tail states located at the a‐Si:H/aSiNx:H interface and in the a‐SiNx:H transitional layer close to the interface, then move to deeper energies in amorphous silicon nitride at longer stress times, larger stress electric fields, or higher stress temperatures. The obtained bias‐stress‐temperature induced threshold voltage shifts are accurately modeled with a stretched‐exponential stress time dependence where the stretched‐exponent β cannot be related to the β=TST/T0 but rather to β≂TST/T0*−β0 for TST≤80 °C; for TST≥80 °C, the β is stress temperature independent. We have al...

Metal semiconductor field effect transistor based on single crystal GaN

Abstract: In this letter we report the fabrication and characterization of a metal semiconductor field effect transistor (MESFET) based on single crystal GaN. The GaN layer was deposited over sapphire substrate using low pressure metalorganic chemical vapor deposition. MESFET devices were fabricated on isolated mesas using TiAu for the source and drain ohmic contacts and silver for the gate Schottky. For devices with a gate length of 4 μm (channel opening, i.e., source to drain separation of 10 μm), a transconductance of 23 mS/mm was obtained at −1 V gate bias. Complete pinch‐off was observed for a gate potential of −12 V.

Method for forming a film and method for manufacturing a thin film transistor

Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250° C. to 400° C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved. Further, when an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity containing gas is regulated so that impurity density becomes larger as approaching to the source electrode and the drain electrode, a leakage current in an OFF-state of the transistor is reduced. Since the impurity containing silicon film is grown by a chemical vapor deposition method in this case, the impurity density thereof can be controlled easily and the control accuracy is also improved.

Thermal imaging using the atomic force microscope

Abstract: We have developed a new and simple technique for thermal imaging with submicrometer spatial resolution using the atomic force microscope. The method is particularly unique for simultaneously obtaining thermal and topographical images of biased electronic devices and interconnects where there could be different materials and potential variations on a scan surface. Application to a biased metal‐semiconductor field‐effect transistor showed the heating under the gate and a hot spot between the gate and drain where the electric field is known to be the highest. Thermal images of a biased polycrystalline Al‐Cu via structure showed the grain boundaries to be hotter than within the grain. With the development of electronic devices and structures in the submicrometer range, this technique can become very useful as a tool for thermal characterization and property measurement.

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Abstract: Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

Silicon carbide power mosfet with floating field ring and floating field plate

Abstract: A silicon carbide power MOSFET device includes a first silicon carbide layer, epitaxially formed on the silicon carbide substrate of opposite conductivity type. A second silicon carbide layer of the same conductivity type as the substrate is formed on the first silicon carbide layer. A power field effect transistor is formed in the device region of the substrate and in the first and second silicon carbide layers thereover. At least one termination trench is formed in the termination region of the silicon carbide substrate, extending through the first and second silicon carbide layers thereover. The termination trench defines one or more isolated mesas in the termination region which act as floating field rings. The termination trenches are preferably insulator lined and filled with conductive material to form floating field plates. The outermost trench may be a deep trench which extends through the first and second silicon carbide layers and through the drift region of the silicon carbide substrate. Since the termination region is formed from the first and second silicon carbide layers in the termination region, a time consuming, high temperature diffusion to form a floating field ring is not necessary. Rather, the same epitaxial first and second silicon carbide layers which are used to form an FET in the device region may also be used to form the floating field ring in the termination region.

Polythienylenevinylene thin‐film transistor with high carrier mobility

Abstract: A thin‐film transistor (TFT) with high carrier mobility has been fabricated using precursor‐route poly(2,5‐thienylenevinylene) (PTV) as semiconductor. The carrier mobility has been determined to be 0.22 cm2/V s, which is in the same level of that of amorphous silicon TFT. It has also been made clear that the carrier mobility is linearly proportional to the conversion ratio from the insulated precursor polymer to π‐conjugated PTV. The π‐conjugation length is crucial to obtain high carrier mobility in π‐conjugated polymer TFT.

Power MOSFET in silicon carbide

Abstract: The power metal oxide semiconductor field effect transistor (MOSFET) has a drain region, a channel region, and a source region formed of silicon carbide. The drain region has a substrate of silicon carbide of a first conductivity type and a drain-drift region of silicon carbide adjacent the substrate having the same conductivity type. The channel region is adjacent the drain-drift region and has the opposite conductivity type from the drain-drift region. The source region is adjacent the channel region and has the same conductivity type as the drain-drift region. The MOSFET has a gate region having a gate electrode formed on a first portion of the source region, a first portion of the channel region, and a first portion of the drain region. A source electrode is formed on a second portion of the source region and a second portion of the channel region. Also, a drain electrode is formed on a second portion of the drain region.

A new drain-current injection technique for the measurement of off-state breakdown voltage in FETs

Abstract: A simple three-terminal technique for measuring the off-state breakdown voltage of FETs is presented. With the source grounded, current is injected into the drain of the on-state device. The gate is then ramped down to shut the device off. In this process, the drain-source voltage rises to a peak and then drops. This peak represents an unambiguous definition of three-terminal breakdown voltage. In the same scan, a measurement of the two-terminal gate-drain breakdown voltage is also obtained. The method offers potential for use in a manufacturing environment, as it is fully automatable. It also enables easy measurement of breakdown voltage in unstable and fragile devices. >

Thin-film transistor and a liquid crystal matrix display device using thin-film transistors of this type

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs

Abstract: An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators. >

Thin-film, flat panel, pixelated detector array for real-time digital imaging and dosimetry of ionizing radiation

Abstract: A thin-film, flat panel, pixelated detector array serving as a real-time digital imager and dosimeter for diagnostic or megavoltage X rays or gamma rays, including a plurality of photodiodes (30) made of hydrogenated amorphous silicon arrayed in columns and rows upon a glass substrate (12). Each photodiode (30) is connected to a thin film field effect transistor (52) also located upon the glass or quartz substrate (12). Upper and lower metal contacts (38, 22) are located below and above the photodiodes (30) to provide the photodiodes (30) with a reverse bias. The capacitance of each photodiode (30) when multiplied by the resistance of the field effect transistor (52) to which it is connected yields an RC time constant sufficiently small to allow fluoroscopic or radiographic imaging in real time.

High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si

Abstract: An enhancement‐mode p‐channel metal‐oxide‐semiconductor field‐effect transistor (PMOSFET) is fabricated on a strained Si layer for the first time. A biaxial strain in a thin Si layer is produced by pseudomorphically growing this layer on a Ge0.25Si0.75 buffer layer which is grown on a Si substrate. At higher magnitude of gate bias, channel mobility of a strained Si PMOSFET has been found to be 50% higher than that of an identically processed conventional Si PMOSFET.

Vertical power MOSFET structure having reduced cell area

Abstract: In a vertical power field effect transistor, a side surface of a gate electrode is covered with a side oxide film, and a groove is formed in self-alignment with the side oxide film to extend from a surface area of a silicon substrate between a pair of adjacent gate electrodes, to reach a base region. A tungsten film is filled into the groove thus formed, and a source electrode-is formed in contact with the tungsten film within the groove.

A novel charge sensitive preamplifier without the feedback resistor

Abstract: A novel charge sensitive preamplifier which has no resistor in parallel with the feedback capacitor is presented. No external device or circuit is required to discharge the feedback capacitor. The detector leakage and signal current flows away through the gate of the first JFET which works with its gate to source junction slightly forward biased. The DC stabilization of the preamplifier is accomplished by an additional feedback loop, which permits to equalize the current flowing through the forward baised gate to source junction and the current coming from the detector. An equivalent noise charge of less than 20 electrons r.m.s. has been measured at room temperature by using an input JFET with a transconductance to gate capacitance ratio of 4 mS/5.4 pF.

Field-effect transistor with perovskite oxide channel

Abstract: A field-effect transistor (FET) is described having a source; a drain; a channel formed between the source and the drain; and a gate electrode. The channel is composed of a film layer of oxide having the perovskite structure comprised of: (1) at least one metal selected from the group consisting of the metal elements in Group IV through Group XI of the Periodic Table of Elements and Bi; and (2) at least one metal selected from the group consisting of alkali metals, alkaline earth metals and rare earth metals. The layer has a film thickness of not larger than 1000 Å and the electrical resistivity not less than 2 million centimeters. The channel of the oxide film layer is provided with a metal oxide insulator layer formed directly or through another metal oxide insulator layer and a gate electrode in electrical contact therewith. It is possible to make memories using this FET. In addition, it also becomes possible to reduce the size of devices using the FET of the invention.

Vertical field effect transistor and diode

Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Method for forming an insulated gate field effect transistor

Abstract: In an inverted stagger type thin-film transistor, the preparing process thereof can be simplified, and the unevenness of the thin film transistor prepared thereby can be reduced That is, disclosed is a preparing method which comprises selectively doping a semiconductor on a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them, or a preparing method which comprises selectively doping the semiconductor region with an impurity by a laser doping method

Field-effect transistor with at least two different semiconductive organic channel compounds

Abstract: A field effect transistor has a channel between a source electrode and a drain electrode made from an organic semiconductor. In one form of the invention, the channel is a mixture of at least two different organic compounds. In another form of the invention, the channel is a lamination of at least two films of different organic compounds. The channel can also be a π-conjugated block copolymer of at least two different types of monomers.

Non-volatile random access memory cell constructed of silicon carbide

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Insulated-gate field-effect transistor structure and method

Abstract: An insulated-gate field-effect transistor 10 is formed on a semiconductor substrate 8. The source 12 and/or drain 20 junction region comprises a heavily doped region 14 (22), a non-overlapped lightly doped region 16 (24), and an overlapped lightly doped region 18 (26). The doping concentration and junction depth of the overlapped 18 and non-overlapped 16 lightly doped regions may be controlled and optimized independently. An insulating layer 50 is formed over a channel region 28 which separates the source 12 and drain 20, and also over the overlapped portions of the source 18 and drain 26. A gate 42 is formed over the insulating layer 50. Two exemplary methods of fabrication are disclosed in detail herein as well as other systems and methods.

Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions

Abstract: The authors point out that time to breakdown (t/sub BD/) of silicon dioxide has a pronounced frequency dependence when it is measured under bipolar bias conditions. At high frequencies, bipolar t/sub BD/, can be enhanced by two orders of magnitude over the t/sub BD/, obtained using DC or unipolar pulse bias of the same frequency and electric field. The lifetime improvement is attributed to detrapping of holes. At high frequencies, the improvement is maximum because the trapped holes are concentrated at the interface where they can easily be removed upon field reversal. At low frequencies, there is less improvement because the trapped hole distribution extends further into the oxide. Two different mechanisms are proposed to explain the frequency-dependent spreading of the trapped hole distribution away from the interface. >

Lateral profiling of oxide charge and interface traps near MOSFET junctions

Abstract: A technique for measuring the lateral distributions of both interface traps and trapped oxide charge near the source/drain junctions in MOSFETs is presented in detail. This technique derives from the charge pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Some illustrative results are given. The various issues involved in its implementation and its practical limitations are discussed. >

High-efficient class F GaAs FET amplifiers operating with very low bias voltages for use in mobile telephones at 1.75 GHz

Abstract: High-efficiency class F GaAs power FET amplifiers working with a very low drain bias voltage of 3 V, for use in portable telephones, are reported. The transistor used has an optimized gate periphery of 2000 mm and a gate length of 0.7 mu m. Under class F operation with a drain voltage of 3 V, it has demonstrated an output power of 24.5 dBm with 71% of power-added efficiency at the operating frequency of 1.75 GHz. Output harmonic levels lower than -25 dBc have been measured. The results obtained present the state of the art as published for low-bias-voltage, low-power-consumption amplifiers for mobile telephone systems. >

Octadecyltrichlorosilane monolayers as ultrathin gate insulating films in metal‐insulator‐semiconductor devices

Abstract: In order to fabricate metal‐insulator‐semiconductor (MIS) devices with gate insulating films thinner than 5.0 nm, organic monolayers have been grafted on the native oxide layer of silicon wafers. We demonstrate that a single monolayer of octadecyltrichlorosilane with a 2.8 nm thickness allows to fabricate a silicon based MIS device with gate current density as low as 10−8 A/cm2 at 5.8 MV/cm, insulator charge density lower than 1010 cm−2, fast interface state density of the order of 1011 cm−2 eV−1, and dielectric breakdown field as high as 12 MV/cm. Moreover, this insulating film is thermally stable up to 450 °C.