Showing papers on "Field-effect transistor published in 1994"

All-polymer field-effect transistor realized by printing techniques

Abstract: A field-effect transistor has been fabricated from polymer materials by printing techniques. The device characteristics, which show high current output, are insensitive to mechanical treatments such as bending or twisting. This all-organic flexible device, realized with mild techniques, opens the way for large-area, low-cost plastic electronics.

Ballistic metal-oxide-semiconductor field effect transistor

Abstract: Experiments on ultra‐small metal‐oxide‐semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra‐small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current‐voltage characteristics of the ballistic n‐channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current‐voltage characteristics in the ballistic transport regime are also investigated for the p‐channel MOSFET, the dual gate ultra‐thin silicon on insulator MOSFET, and the high electron mobility transistor device. The obtained current gives the maximum current limitation of each field effect transistor geometry. The current control mechanism of ballistic MOSFETs is discussed. The current value is governed by the product of the carrier density near the source edge in the channel, and the velocity with which carriers are injected from the source into the channel.Influence of optical phonon emission to the transport is discussed. It is suggested that if the device is operated with relatively low carrier density at low temperatures, and if the scattering processes other than the optical phonon emission are suppressed so as to attain the ballistic transport, the optical phonon emission is also suppressed and ballistic transport is sustained. A convenient figure of merit to show the ballisticity of carrier transport in an experimental MOSFET is proposed. Its value is estimated for some examples of the recent ultra‐small MOSFET experiment. The proposed current voltage characteristics are evaluated for a dual gate silicon on insulator MOSFET geometry. The result is compared with the recently reported elaborate Monte Carlo simulation with satisfactory agreement.

SiC devices: physics and numerical simulation

Abstract: The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n/sup -/-n/sup +/ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 /spl Omega/cm/sup 2/, while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4/spl times/10/sup 6/ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations. >

Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors

Abstract: Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/ Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si Similar enhancements are observed in the device transconductance In addition, buried channel devices show peak room temperature mobilities about three times that of control devices >

Electron Mobility Enhancement in S trained-Si N-Type Metal-Oxide- S emiconductor Field-Effect Transistors

Abstract: Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si1 -zGez. Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si. Surface channel devices show low-field mobility enhancements of 80% at mm temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si. Similar enhancements are observed in the device transconductance. In addition, buried channel devices show peak room temperature mobilities about three times that of control devices.

Microwave performance of a 0.25 μm gate AlGaN/GaN heterostructure field effect transistor

Abstract: We fabricated a 0.25 μm gate length AlGaN/GaN heterostructure field effect transistor (HFET) with a maximum extrinsic transconductance of 27 mS/mm (at room temperature) limited by the source series resistance. The device exhibited an excellent pinch‐off and a low parasitic output conductance in the saturation regime. We measured the cutoff frequency fT and the maximum oscillation frequency fmax as 11 and 35 GHz, respectively. These values are superior to the highest reported values for field effect transistors based on other wide band‐gap semiconductors such as SiC. These results demonstrate an excellent potential of AlGaN/GaN HFETs for microwave and millimeter wave applications.

Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures

Abstract: Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation. >

SiGe-channel heterojunction p-MOSFET's

Abstract: The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n/sup +/ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n/sup +/-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm/sup 2//V.s at 300 K and 980 cm/sup 2//V.s at 82 K are obtained. >

Evaluation of a dual bias dual metal oxide-silicon semiconductor field effect transistor detector as radiation dosimeter

Abstract: A new type of direct reading semiconductordosimeter has been investigated as a radiation detector for photon and electron therapy beams of various energies. The operation of this device is based on the measurement of the threshold voltage shift in a custom‐built metal oxide‐silicon semiconductorfield effect transistor(MOSFET). This voltage is a linear function of absorbed dose. The extent of the linearity region is dependent on the voltage controlled operation during irradiation. Operating two MOSFETS at two different biases simultaneously during irradiation will result in sensitivity (V/Gy) reproducibility better than ±3% over a range in dose of 100 Gy and at a dose per fraction greater than 20×10−2 Gy. The modes of operation give this device many advantages, such as continuous monitoring during irradiation, immediate reading, and permanent storage of total dose after irradiation. The availability and ease of use of these MOSFETdetectors make them very promising in clinical dosimetry.

Series-parallel association of FET's for high gain and high frequency applications

Abstract: This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

Abstract: A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V. >

Current/voltage characteristic collapse in AlGaN/GaN heterostructure insulated gate field effect transistors at high drain bias

Abstract: The authors describe the current/voltage characteristic collapse under a high drain bias in AlGaN/GaN heterostructure insulated gate field effect transistors (HIGFETs) grown on sapphire substrates. These devices exhibit a low resistance state and a high resistance state, before and after the application of a high drain voltage, respectively. At room temperature, the high resistance state persists for several seconds. The device can also be returned into the low resistance state by exposing it to optical radiation. Electron trapping in the gate insulator near the drain edge of the gate is a possible mechanism for this effect, which is similar to what has been observed in AlGaAs/GaAs HFETs at cryogenic temperatures.

Complementary junction heterostructure field-effect transistor

Abstract: A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers

Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films

Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a semiconductor film on a substrate, oxidizing a surface of said semiconductor film in an oxidizing atmosphere with said semiconductor film heated or irradiated with light, and further depositing an oxide film on the oxidized surface of the semiconductor film by PVD or CVD The first oxide film has a good interface condition with the semiconductor film and a characteristics of an insulated gate field effect transistor can be improved if the first oxide film and the second oxide film are used as a gate insulating film

Silicon field-effect transistor based on quantum tunneling

Abstract: This letter explores regulation of current flow within a silicon field‐effect transistor by gate‐induced tunneling through a Schottky barrier located at the interface between a metallic source electrode and the Si channel. The goal here is to forestall short‐channel effects which are expected to prevent further size reductions in conventional devices when linewidths reach ∼1000 A. Control of tunneling appears to be possible at minimum channel lengths L∼250 A or less while simultaneously eliminating the need for large‐area source and drain contacts, so that scaling of Si transistors could be significantly extended if this principle proves technically feasible.

A capacitorless dram device on silicon-on-insulator substrate

Abstract: A DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22). A second (16) and a third (14) semiconductor region of the opposite conductivity are formed in the first semiconductor region (18). A fourth semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed within the second semiconductor region (16) with higher doping concentration. A insulating layer (11) is formed on the semiconductor surface. On top of the insulating layer (11), a gate electrode (10) is formed and is at least partially overlapped with the first (18), the second (16), the third (14), and the fourth (12) semiconductor region. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and the third (14) semiconductor region where the information is stored. The amount of charge stored in the storage node (24) is controlled by a first transistor including the fourth semiconductor region (12), the second semiconductor region (16), the storage node (24), and the gate electrode (10).

Modeling of ultrathin double-gate nMOS/SOI transistors

Abstract: An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >

Enhancement mode metal‐semiconductor field effect transistors using homoepitaxial diamonds

Abstract: Enhancement mode‐type metal‐semiconductor field effect transistors using diamond have been fabricated. The transistor operation is based on the control of surface p‐type conduction of a hydrogen terminated homoepitaxial layer. Boron doping was not used for the conduction. An aluminum contact is used for the Schottky gate and gold ohmic contacts are used for the source and drain. The obtained transconductance is 20–200 μs/mm using aluminum gates of 10–40 μm in length. The active region on the homoepitaxial layer is thin enough for the total depletion of carriers when the gate bias is zero.

MOSFET thermal noise modeling for analog integrated circuits

Abstract: The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements. >

Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability

Abstract: The origin of the substrate current of a metal‐oxide‐semiconductor field‐effect transistor when the gate oxide undergoes Fowler–Nordheim stress is investigated. It is also shown that anode hole injection current predicts the breakdown of silicon dioxide between 25 and 130 A and 2.4 and 12 V. While the measured substrate current is entirely due to anode hole injection for oxides thicker than 55 A, tunneling by valence‐band electrons contributes to the substrate current in thinner oxides. Valence‐band electron tunneling current is shown to increase with oxide stressing similar to low‐voltage gate oxide leakage; apparently, both are enhanced by trap‐assisted tunneling. For oxides of thickness between 25 and 130 A, the theory of anode hole injection directly verified for oxides thicker than 55 A is able to model silicon dioxide breakdown accurately.

Method for forming a field-effect transistor including anodic oxidation of the gate

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Random telegraph signals in deep submicron n-MOSFET's

Abstract: Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO/sub 2/ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel. >

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

Abstract: This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

Semiconductor device with an MOST provided with an extended drain region for high voltages

Abstract: The invention relates to a semiconductor device with a semiconductor body (1) comprising a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which comprises a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e . the drain extension region (6) comprises a number of zones (25) of the second conductivity type which extend from the channel region (7) to the drain region (5) and which have a width (26) and doping concentration such that, when the voltage difference across the blocked pn junction (28) between the surface region (3) and the drain extension region (6) is increased, the drain extension region (6) is fully depleted at least locally before drain breakdown occurs. The measure according to the invention renders it possible to choose the number and the width (26) of the zones (25) as an additional parameter of the device. It is a surprise to find that devices according to the invention have comparatively high drain breakdown voltages and comparatively low on-resistances which cannot be realised with a continuous drain extension region (6).

Ultra‐low‐temperature growth of high‐integrity gate oxide films by low‐energy ion‐assisted oxidation

Abstract: The gate oxide films have been grown at a temperature as low as 450 °C by direct oxidation of silicon. Such a low‐temperature oxidation has been realized by employing a precision controlled ion bombardment in an Ar/O2 mixed plasma for the surface activation. Perfectly controlled Ar ions give the bombardment energy for the oxide film growth. Dielectric breakdown fields of 10 MV/cm are achieved. Integration in a total low‐temperature device process has been demonstrated by fabricating self‐aligned Al‐gate metal‐oxide‐silicon field effect transistor (MOSFET) formed without any heat processing over 450 °C. The precise control of the ion bombardment is quite essential for the low‐temperature process.

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

Abstract: The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect. >

PCIM: a physically based continuous short-channel IGFET model for circuit simulation

Abstract: We present an accurate analytical IGFET model (PCIM), for short-channel devices down to sub-half micron channel lengths. The model is described by a single drain current equation, valid for both weak and strong inversion regions of device operation. The model contains a new velocity-field (/spl upsi/-/spl epsi/) relation for carriers in the channel region. Combining this relation with the channel length modulation expression, obtained using engineering approximations to the two-dimensional fields near the drain end in saturation, results in an accurate drain conductance equation. The value for the carrier saturated velocity extracted from the I-V data for different CMOS technologies is 7-8/spl times/10/sup 6/ cm/s for electrons and 5-6/spl times/10/sup 6/ cm/s for holes, consistent with the reported values. The model not only predicts accurate output conductance, which is important for analog design, but also accurately simulates intrinsic gate capacitances for short channel devices. Since the model is inherently continuous, device conductances and capacitances are smooth and continuous at the transition points. This continuity results in enhanced convergence properties of the circuit simulator SPICE. Because the model is physically based, the temperature dependence of device characteristics in the temperature range 0-120/spl deg/C can easily be predicted simply by taking the temperature dependence of the threshold voltage, carrier mobility and velocity saturation parameters. >