Showing papers on "Field-effect transistor published in 1996"

A ferroelectric transparent thin‐film transistor

Abstract: Operation is demonstrated of a field‐effect transistor made of transparant oxidic thin films, showing an intrinsic memory function due to the usage of a ferroelectric insulator. The device consists of a high mobility Sb‐doped n‐type SnO2 semiconductor layer, PbZr0.2Ti0.8O3 as a ferroelectric insulator, and SrRuO3 as a gate electrode, each layer prepared by pulsed laser deposition. The hysteresis behavior of the channel conductance is studied. Using gate voltage pulses of 100 μs duration and a pulse height of ±3 V, a change of a factor of two in the remnant conductance is achieved. The dependence of the conductance on the polarity of the gate pulse proves that the memory effect is driven by the ferroelectric polarization. The influence of charge trapping is also observed and discussed.

Fast and long retention-time nano-crystal memory

Abstract: A threshold-shifting, single transistor memory structure with fast read and write times and long retention time is described. The structure consists of a silicon field-effect transistor with nano-crystals of germanium or silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 2-5 nm size nano-crystals which are separated from each other by greater than 5 nm of SiO/sub 2/ and from the inversion layer of the substrate surface by less than 5 nm of SiO/sub 2/. Direct tunneling of charge from the inversion layer and its storage in the nano-crystal causes a shift in the threshold voltage which is detected via current sensing. The nano-crystals are formed using implantation and annealing or using direct deposition of the distributed floating gate region. Threshold shift of 0.3 V is obtained in Ge-implanted devices with 2 nm of SiO/sub 2/ injection layer by a 4 V write pulse of 300 ns duration. The nano-crystal memories achieve improved programming characteristics as a nonvolatile memory as well as simplicity of the single poly-Si-gate process. The V/sub T/ window is scarcely degraded after greater than 10/sup 9/ write/erase cycles or greater than 10/sup 5/ s retention time. Nano-crystal memories are promising for nonvolatile memory applications.

Room temperature operation of a single electron transistor made by the scanning tunneling microscope nanooxidation process for the TiOx/Ti system

Abstract: The single electron transistor (SET) is fabricated using the scanning tunneling microscope (STM) as a fabrication process, and the fabricated SET operates at room temperature. Using the STM tip as a cathode, the surface of the titanium metal can be oxidized, and the few tens of nanometer wide oxidized titanium line can be made. The small island region of the SET of ∼30×∼35 nm2 is formed by the oxidized titanium line. The Coulomb staircase of 150 mV period is observed in the current–voltage characteristics of the SET at room temperature.

Very high breakdown voltage and large transconductance realized on gan heterojunction field effect transistors

Abstract: We report record high breakdown voltages up to 340 and 230 V realized on unintentionally doped (1.5 μm gate length) and Si doped (1 μm gate length) AlGaN/GaN modulation doped field effect transistors (MODFETs), respectively. The devices also have large transconductances up to 140 mS/mm and a full channel current of 150–400 mA/mm. The Si doped MODFET sample demonstrated a very high room temperature mobility of 1500 cm2/Vs. With these specifications, GaN field effect transistors as microwave power devices are practical.

Intrinsic Transport Properties and Performance Limits of Organic Field-Effect Transistors

Abstract: The field-effect mobility in thin-film transistors based on α-sexithiophene (α-6T) and related materials displays a temperature dependence that is remarkably nonmonotonic. Above a transition temperature T T (specific to a given material) the transport is thermally activated, whereas below T T there is a very steep enhancement of the mobility. In the activated regime, the results are well described by the theoretical predictions for small polaron motion made by Holstein in 1959. An analysis of the transistor characteristics shows that the hopping transport in these devices is intrinsic. Performance limits for devices based on α-6T and related materials were established; these limits point to the strong possibility that better molecular materials for transistor applications may be designed from first principles.

Magnetic spin injected field effect transistor and method of operation

Abstract: A new hybrid magnetic spin injected-FET structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid FET uses ferromagnetic materials for the source and drain, and like a conventional FET, has two operating states determined by a gate voltage, "off" and "on". The ferromagnetic layers of the hybrid FET are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the "on" state the spin injected FET has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic source and drain. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the drain to be parallel or antiparallel with that of the source, thus changing the resistance of the device to a current of spin polarized electrons injected into the source and flowing to the drain through the channel under the gate. The new FET can be used as a memory cell because the drain magnetization is non-volatile, and can represent a binary data value to be stored in the cell. A conductive write line can be used for inductively coupling an input magnetic field (representing a data value to be stored in the device) with the drain magnetization to alter the orientation state of the latter. An array of spin injected FETs can be coupled together in an array to form a new hybrid FET memory array. The new FET can also be used as a logic gate that stores the result of a boolean function. A magnetic field generated by the combined current of one or more input data signals is coupled to the spin injected FET. Depending on the particular function to be implemented, the ferromagnetic drain magnetization can be configured to change or retain its orientation based on particular predefined combinations of input data signals.

Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors

Abstract: We report on the fabrication and characterization of Al0.1Ga0.9N/GaN heterojunction field effect transistors, both an enhancement mode and a depletion mode with a low pinchoff voltage, suitable for digital integrated circuit applications. For an enhancement mode device with a 1 μm gate length and 5 μm drain‐to‐source separation, the dc transconductance is around 23 mS/mm. Connecting the enhancement mode device as a switching transistor and a depletion mode device as a load, we demonstrate an AlGaN/GaN inverter.

Precursor route pentacene metal-insulator-semiconductor field-effect transistors

Abstract: Metal‐insulator‐semiconductor field‐effect transistors have been constructed with pentacene as the active semiconductor. The pentacene is processed by spin coating from a soluble precursor. A simple thermal conversion yields transistors with carrier mobilities as high as 9×10−3 cm2 V−1 s−1 and current modulations of the order of 105. Depletion of charge is essential to the device operation. Data for an invertor exhibiting voltage amplification are presented.

Coulomb blockade oscillations at room temperature in a Si quantum wire metal‐oxide‐semiconductor field‐effect transistor fabricated by anisotropic etching on a silicon‐on‐insulator substrate

Abstract: We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a separation‐by‐implanted‐oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. The oscillations split into several sharp peaks when the temperature is decreased, indicating that the channel is separated by several serial coupled quantum dots and that the quantum levels of these dots correspond to the observed fine peaks.

Ion‐implanted GaN junction field effect transistor

Abstract: Selective area ion implantation doping has been used to fabricate GaN junction field effect transistors (JFETs). p‐type and n‐type doping was achieved with Ca and Si implantation, respectively, followed by a 1150 °C rapid thermal anneal. A refractory W gate contact was employed that allows the p‐gate region to be self‐aligned to the gate contact. A gate turn‐on voltage of 1.84 V at 1 mA/mm of gate current was achieved. For a ∼1.7 μm×50 μm JFET with a −6 V threshold voltage, a maximum transconductance of 7 mS/mm at VGS=− 2V and saturation current of 33 mA/mm at VGS=0 V were measured. These results were limited by excess access resistance and can be expected to be improved with optimized n+ implants in the source and drain regions.

Leakage current and electrical breakdown in metal‐organic chemical vapor deposited TiO2 dielectrics on silicon substrates

Abstract: The leakage current through 190 A TiO2 deposited through metal‐organic chemical vapor deposition on p‐type silicon substrates has been measured as a function of temperature for both accumulation and inversion biases. When biased into inversion, the current initially is temperature independent, suggesting that the current in this regime is dominated by tunneling. Above 100 °C however it shows standard thermionic emission behavior up to 160 °C where it again becomes temperature independent. The leakage under accumulation bias was independent of temperature up to 70 °C while it shows standard thermionic emission behavior. The barrier for emission was between 0.94 and 1.0 eV for all samples measured. Both ramped voltage and time dependent dielectric breakdown measurements were carried out on these films. The lack of a breakdown event in constant current stress suggests that these films may be extremely robust as gate dielectrics in future metal‐oxide‐semiconductor field‐effect transistors.

Organic field-effect bipolar transistors

Abstract: Organic field‐effect transistors (FETs) which employ two carefully selected active materials can function as n channel, p channel, or both n‐ and p‐channel devices. It is shown that under an appropriate set of bias conditions the channel current in FETs with α‐hexathienylene (α‐6T) and C60 active layers consist of electron and hole components that are injected from the source and drain contacts into the C60 and α‐6T layers, respectively.

Unified complete MOSFET model for analysis of digital and analog circuits

Abstract: In this paper, we describe a complete MOSFET model developed for circuit simulation based on fully consistent physical concept. The model describes all transistor characteristics as a function of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. Contrary to the expectation, the results show that our semi-implicit model including the iteration procedures can even reduce the CPU time significantly in comparison with a conventional model similar to BSIM2 including short-channel effects. This is due to the consistent description of the model equations for all transistor characteristics, which results in more straightforward device equations, once the surface potentials have been computed.

Complementary circuits with organic transistors

Abstract: The operating characteristics of complementary inverters with n‐channel napthalenetetracarboxylic dianhydride thin‐film transistors (TFTs) and p‐channel transistors with hole transporting organic active materials are described. The n‐channel TFTs have been used as the load in one circuit configuration and as the driver in the second configuration.

CW operation of short-channel GaN/AlGaN doped channel heterostructure field effect transistors at 10 GHz and 15 GHz

Abstract: We report on a 0.15-/spl mu/m gate length AlGaN/GaN doped channel heterostructure field effect transistor (DC-HFET) with maximum frequency of oscillation in excess of 97 GHz. HFETs based on our doped channel design exhibited CW microwave operation up to 15 GHz with a maximum output power of approximately 270 mW/mm at 10 GHz. These values are still limited by parasitics and can be significantly improved by optimizing the device design.

High transconductance heterostructure field‐effect transistors based on AlGaN/GaN

Abstract: We report on the fabrication and characterization of Al0.15Ga0.85N/GaN heterostructure field‐effect transistors (HFETs) with transconductance as high as 120 mS/mm and saturated current density of 0.35 A/mm for a device with a gate length and width of 1 and 100 μm. This represents one of the best results for such device. A comparison of the maximum transconductance of devices on wafers with different channel conductance is presented to analyze the factors limiting the performance. Our data indicates the series resistance between the source and drain to be the limiting factor for the maximum dc transconductance.

Neuron adhesion on a silicon chip probed by an array of field-effect transistors.

Abstract: Adhesion of neurons to surfaces in biological tissue (eg, to glia cells, in synapses) or in cell culture (on glass or silicon) may seriously change the features of the electrical signals Transmembrane ion currents have to flow along the narrow cleft between membrane and surface They give rise to a drop of voltage that may affect, in turn, the ion channels [1] In the present paper we show that the electrical properties of cell adhesion can be probed by taking advantage of the neuron-silicon junction [2,3] We place the neuron on an oxidized surface of silicon with an integrated array of field-effect transistors with open metal-free gate oxide [cf Fig 1(a)] An ac voltage is applied to the neuron This voltage couples into the cleft through the conductance and the capacitance of the membrane The resulting extracellular voltage profile is evaluated from the modulation of the source-drain currents Neuron-silicon assembly— A view of the silicon chip is shown in Fig 2(a) The 16 metal-free transistors are arranged in two rows Their distance is 52 mm The area of the transistor channels is 18 mm 3 18 mm Zones of recessed oxide separate the transistors (They give rise to a modulation of the surface profile by about 250 nm) Each drain has its own lead All transistors share a common source Care was taken that the geometric aspects and the electrical properties (bias voltages, sensitivity, and threshold voltage) of the transistors were similar to the larger transistors, used in previous experiments [2,3] The chip s10 mm 3 10 mmd was stuck on a plate with copper leads After wedge bonding a Plexiglas chamber was attached We cleaned the exposed surface of the chip by hot basic hydrogen peroxide The gate region was coated with poly-L-lysine The chamber was filled with culture medium (Leibowitz-15) Retzius cells from the segmental ganglia of the leech hirudo medicinalis were isolated [4] and treated with collagenase and dispase before the experiment Then a neuron was placed on the array as illustrated in Fig 2(b) We kept the bath on ground potential using an AgyAgCl electrode [cf Fig 3(b)] A bias voltage of VES › 230 V was applied between electrolyte and bulk silicon The source was kept at bulk potential The drain-source voltage was VDS › 220 V, which caused a source-drain current of about ID › 50 mA A change DVES › 10 mV of the voltage between electrolyte and source induced a current modulation of DID › 2045 mA as checked before the attachment of a neuron The neuron was contacted with a AgyAgCl electrode by fusing the membrane with a patch pipette filled with electrolyte [3,5] The intracellular potential was held at ‐50 mV Cell impedance—We superposed ac stimuli of 15 mV amplitude to the holding potential No action potentials were elicited under these conditions We measured the complex amplitudes V P of the voltage and I P of the current at the head of the pipette [Fig 3(a)] using two lock-in amplifiers A Nyquist plot of the impedance Z › V P yI P of an attached neuron is shown in Fig 3(b) in a frequency range from 1 to 15 000 Hz The double

Methods to enhance SOI SRAM cell stability

Abstract: Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range. Alternatively, or additionally, the discharge of deselected cells can be slowed to avoid instability by increasing resistance of the transistors in the data buffer (with saving of chip space) and/or increasing bit line capacitance by increasing bit line length (allowing increased memory array size or an additional cell array on a chip).

A Josephson field effect transistor using an InAs‐inserted‐channel In0.52Al0.48As/In0.53Ga0.47As inverted modulation‐doped structure

Abstract: A Josephson field effect transistor (JOFET) was coupled with a two‐dimensional electron gas in a strained InAs quantum well inserted into an In0.52Al0.48As/In0.53Ga0.47As inverted modulation‐doped structure. The characteristics of this JOFET are much improved over previous devices by using a high electron mobility transistor (HEMT)‐type gate instead of the usual metal‐insulator‐ semiconductor (MIS)‐type gate. The superconducting critical current as well as the junction normal resistance are completely controlled via a gate voltage of about −1 V; this provides voltage gain over 1 for a JOFET.

TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon?

Abstract: To reduce susceptibility to punchthrough, the channel region of the P body region (104) of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon (101). As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low RDSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer (103, 102) upon which the lightly doped epitaxial layer is formed.

Method for making single and double gate field effect transistors with sidewall source-drain contacts

Abstract: The present invention concerns single-gate and double-gate field effect transistors having a sidewall source contact and a sidewall drain contact, and methods for making such field effect transistors. The channel of the present field effect transistors is raised with respect to the support structure underneath and the source and drain regions form an integral part of the channel.

Trenched field effect transistor with PN depletion barrier

Abstract: A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

C70 thin film transistors

Abstract: Organic semiconductors are being tested as the active electronic elements of thin film field effect transistors (TFTs) and light-emitting diodes. The basis for understanding the criteria for materials selection in organic TFTs is currently quite primitive, and in order to provide information on this question, the present work reports a study of TFTs fabricated from C{sub 70}. The fullerenes C{sub 60} and C{sub 70} are found to exhibit markedly different performances as the active semiconductor in TFT devices. 15 refs., 3 figs.

SOI FET design to reduce transient bipolar current

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike. As applied to an SOICMOS SRAM, the transistor structure including such a gap is effective in suppressing half-select write disturb effects while maintaining the benefits of excess charge storage and floating body effects in the transistor.

Dynamics of power MOSFET switching under unclamped inductive loading conditions

Abstract: The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p/sup +/ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions.

EEPROM having coplanar on-insulator FET and control gate

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Punch-through field effect transistor

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region (44) and drain region (40). Forward conduction occurs through an inversion region between the source region (44) and drain region (40). Blocking is achieved by a gate controlled depletion barrier. Located between the source (44) and drain (40) regions is a fairly lightly doped body region (42). The gate electrode (52A), located in a trench (50A), extends through the source (44) and body (42) regions and in some cases into the upper portion of the drain region (40). The dopant type of the polysilicon gate electrode (52A) is the same type as that of the body region (42). The body region (42) is a relatively thin and lightly doped epitaxial layer grown upon a higly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Thin gate oxide damage due to plasma processing

Abstract: Plasma processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modelled as damage produced by constant-current (or voltage) electrical stress. Plasma processing causes MOSFET parameter degradation, from which one can deduce the plasma charging current. Since the scattering of post-damage device parameters is due to a reproducible variation of stress current across the wafer, one can easily analyse the effect of device geometry on damage by comparing test structures in the same die rather than the averages over a wafer. We have developed a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of the charging current. The model successfully predicts the oxide thickness dependence of plasma charging. It is shown that plasma acting on a very thin oxide during processing may be modelled essentially as a current source. Thus the damage will not be greatly exacerbated as the oxide thickness is further reduced in the future. Although annealing in forming gas can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. The protection diode should be forward biased during processing to safely protect the gate oxide. In CMOS circuits, the drains of the driver circuit can generally act as adequate protection diodes for the oxide regardless of N or P substrate and the polarity of the plasma charging current. The plasma stress current can be reduced by reducing the ion density, which is unfortunately linked to the etch rate or directionality, or by reducing the electron temperature. Maintaining a very uniform plasma over the surface of the wafer, reducing the plasma charging current during the over-etch time and judicious use of protection diode and antenna design rules will reduce plasma damage to an acceptable level for ULSI production even for very thin gate oxides.

Semiconductor device having an insulated gate field effect thin film transistor

Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.