Showing papers on "Field-effect transistor published in 1997"

CMOS scaling into the nanometer regime

Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

High-performance plastic transistors fabricated by printing techniques

Abstract: A printed field-effect transistor (FET) is reported, in which all the essential components are screen-printed for the first time. This transistor has a polyimide dielectric layer, a regioregular poly(3-alkythiophene) semiconducting layer, and two silver electrodes, all of which are printed on an ITO-coated plastic substrate.

Ferroelectric Field Effect Transistor Based on Epitaxial Perovskite Heterostructures

Abstract: Ferroelectric field effect devices offer the possibility of nonvolatile active memory elements. Doped rare-earth manganates, which are usually associated with colossal magnetoresistive properties, have been used as the semiconductor channel material of a prototypical epitaxial field effect device. The carrier concentration of the semiconductor channel can be "tuned" by varying the manganate stochiometry. A device with La0.7Ca0.3MnO3 as the semiconductor and PbZr0.2Ti0.8O3 as the ferroelectric gate exhibited a modulation in channel conductance of at least a factor of 3 and a retention loss of 3 percent after 45 minutes without power.

Micromechanical switches fabricated using nickel surface micromachining

Abstract: Micromechanical switches have been fabricated in electroplated nickel using a four-level surface micromachining process. The simplest devices are configured with three terminals, a source, a drain, and a gate and are 30 /spl mu/m wide, 1 /spl mu/m thick, and 65 /spl mu/m long. A voltage applied between the gate and source closes the switch, connecting the source to the drain. Devices switch more than 10/sup 9/ cycles before failure and exhibit long-lifetime hot switching currents up to 5 mA. The initial contact resistance is less than 50 m/spl Omega/. The breakdown (stand-off) voltage between the source and the drain is greater than 100 V and the off-current is less than 20 fA at 100 V.

Intrinsic MOSFET parameter fluctuations due to random dopant placement

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.

Silicon carbide metal-insulator semiconductor field effect transistor

Abstract: A silicon carbide metal-insulator semiconductor field effect transistor having a u-shaped gate trench and an n-type silicon carbide drift layer. A p-type region is formed in the silicon carbide drift layer and extends below the bottom of the u-shaped gate trench so as to prevent field crowding at the corner of the gate trench. A unit cell of a metal-insulator semiconductor transistor having a bulk single crystal silicon carbide substrate of n-type conductivity silicon carbide. A first epitaxial layer of n-type conductivity silicon carbide and a second epitaxial layer of p-type conductivity silicon carbide formed on the first epitaxial layer. A first trench is formed which extends downward through the second epitaxial layer and into the first epitaxial layer. A second trench, adjacent the first trench, is also formed extending downward through the second epitaxial layer and into the first epitaxial layer. A region of n-type conductivity silicon carbide is formed between the first and second trenches and having an upper surface opposite the second epitaxial layer. An insulator layer is formed in the first trench where the upper surface of the gate insulator layer formed on the bottom of the first trench is below the lower surface of the second epitaxial layer. A region of p-type conductivity silicon carbide is formed in the first epitaxial layer below the second trench. Gate and source contacts are formed in the first and second trenches respectively and a drain contact is formed on the substrate. Preferably the gate insulator layer is an oxide such that the transistor formed is a metal-oxide field effect transistor.

Trapping of photogenerated carriers by InAs quantum dots and persistent photoconductivity in novel GaAs/n-AlGaAs field-effect transistor structures

Abstract: The trapping of photogenerated carriers by embedded InAs quantum dots (QDs) has been studied at 77 K in novel GaAs/n-AlGaAs structures. It is found that the concentration Ns of two dimensional electrons at a given gate voltage Vg is persistently increased by light illumination, because of the trapping of holes by QDs. By the interplay of the gate voltage and photocarrier generation, a distinct hysteresis is observed in the Ns-Vg characteristics. A drastic change of electron mobility by a factor of 19 is achieved by light illumination. The applications of this device for a novel light-controllable floating dot memory is suggested.

Si-SiGe semiconductor device and method of fabricating the same

Abstract: A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.

Semiconductor device including active matrix circuit

Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors

Abstract: We describe physically based analytical models for n‐channel amorphous silicon thin film transistors and for n‐ and p‐channel polysilicon thin film transistors. The models cover all regimes of transistor operation: leakage, subthreshold, above‐threshold conduction, and the kink regime in polysilicon thin film transistors. The models contain a minimum number of parameters which are easily extracted and can be readily related to the structural and material properties of the thin film transistors. The models have been verified for a large number of devices to scale properly with device geometry.

Insulated gate field effect transistor and its manufacturing method

Abstract: An insulated gate field effect transistor is constructed by first forming a non-single crystalline semiconductor layer or island on an insulating surface of a substrate. A gate insulating layer is then formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. An impurity is added to a portion of the semiconductor layer to form source and drain regions, and the semiconductor layer is irradiated with light through the gate insulating layer. In preferred embodiments, the substrate is maintained at a temperature less than 400° C. and the light have a wavelength of 250-600 nm.

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Abstract: A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Demonstration of enhancement-mode p- and n-channel GaAs MOSFETS with Ga2O3(Gd2O3) As gate oxide

Abstract: We report the demonstration of both enhancement-mode p - and n -channel GaAs metal oxide semiconductor field effect transistors (MOSFETs) on GaAs semi-insulating substrates using high quality Ga 2 O 3 (Gd 2 O 3 ) as the gate dielectric and the conventional ion-implant technology. The source and drain regions were selectively implanted with Zn or Si for low resistance ohmic contacts for p - or n -MOSFETs, respectively. AuBe/Pt/Au, Ge/Mo/Au-Ge/Mo/Au, and Ti/Pt/Au were deposited for p - and n -ohmic contacts and gate electrode, respectively. The devices, with a 4 × 50 μ m 2 gate geometry, exhibit an extrinsic transconductance of 0.18 and 0.1 mS/mm for p - and n -MOSFETs, respectively, and an excellent gate breakdown field greater than 3 MV cm −1 .

Room temperature operation of Si single-electron memory with self-aligned floating dot gate

Abstract: We have developed an excellent fabrication method for a Si single-electron field effect transistor memory device having a self-aligned floating dot gate. This device demonstrates single electron memory operation at room temperature. The ability to precisely control the size and position of the floating dot gate and the channel indicates the feasibility of practical single-electron memory.

A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channel

Abstract: We have demonstrated a room-temperature silicon single-electron transistor memory that consists of (i) a narrow channel metal-oxide–semiconductor field-effect transistor with a width (∼10 nm) smaller than the Debye screening length of single electron; and (ii) a nanoscale polysilicon dot (∼7×7 nm) as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can significantly screen the channel from the potential on the control gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the threshold shift, and a self-limiting charging process.

Pass gate circuit with body bias control

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers

Abstract: A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

Thin-film field-effect transistor with organic semiconductor requiring low operating voltages

Abstract: A thin film transistor (TFT) device structure based on an organic semiconductor material, that exhibits a high field effect mobility, high current modulation and a low sub-threshold slope at lower operating voltages than the current state of the art organic TFT devices. The structure comprises a suitable substrate disposed with he following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the unexpected gate voltage dependence of the organic semiconductor to achieve high field effect mobility levels at very low operating voltages. Judicious combinations of the choice of this insulator material and the means to integrate it into the TFT structure are taught that would enable easy fabrication on glass or plastic substrates and the use of such devices in flat panel display applications.

Nanoscale field-effect transistors: An ultimate size analysis

Abstract: We have used a simple, analytically solvable model to analyze the characteristics of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10 nm-scale channel length L. The model assumes ballistic dynamics of two-dimensional electrons in an undoped channel between highly doped source and drain. When applied to silicon n-MOSFETs, calculations show that the voltage gain (necessary for logic applications) drops sharply at L∼10 nm, while the conductance modulation remains sufficient for memory applications until L∼4 nm.

Short channel self-aligned VMOS field effect transistor

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

Abstract: A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.

Full-wave rectifier and method of operation for a recognition system

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (VDD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).

Dual material gate field effect transistor (DMGFET)

Abstract: A new type of device, the dual material gate field effect transistor (DMGFET), is presented for the first time The gate of the DMGFET consists of two laterally contacting materials with different work functions This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain, resulting a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short channel effects

Field effect transistor with nitride compound

Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.

Comparison of TiSi2 , CoSi2, and NiSi for Thin‐Film Silicon‐on‐Insulator Applications

Abstract: TiSi2, CoSi2, and NiSi self-aligned silicide processes have been studied, compared, and applied to thin-film silicon-on-insulator technology. Compared to TiSi2, CoSi2 and NiSi have the advantages of wider process temperature window, no significant doping retarded reaction, narrow runner degradation, and thin-film degradation. Therefore, they are more suitable for thin-film silicon-on-insulator technology. N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for low-voltage, low-power microwave applications. The initial thicknesses of titanium, cobalt, and nickel are 30, 13, and 25 nm, respectively. The gate sheet resistances are 6.2, 4.4, and 2.9 Omega/square, respectively, and the total source/drain series resistances are 700, 290, and 550 Omega mu m, respectively. High-frequency measurement results are also presented.

Si/SiGe vertical junction field effect transistor

Abstract: A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

MOSFET having buried shield plate for reduced gate/drain capacitance

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.